main.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 00000f86 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000198 00800060 00000f86 0000101a 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000005 008001f8 008001f8 000011b2 2**0 ALLOC 3 .noinit 00000000 008001fd 008001fd 000011b2 2**0 CONTENTS 4 .eeprom 00000000 00810000 00810000 000011b2 2**0 CONTENTS 5 .stab 00001ce0 00000000 00000000 000011b4 2**2 CONTENTS, READONLY, DEBUGGING 6 .stabstr 00000d0b 00000000 00000000 00002e94 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 4a 00 jmp 0x94 4: 0c 94 65 00 jmp 0xca 8: 0c 94 65 00 jmp 0xca c: 0c 94 65 00 jmp 0xca 10: 0c 94 65 00 jmp 0xca 14: 0c 94 65 00 jmp 0xca 18: 0c 94 65 00 jmp 0xca 1c: 0c 94 65 00 jmp 0xca 20: 0c 94 65 00 jmp 0xca 24: 0c 94 65 00 jmp 0xca 28: 0c 94 65 00 jmp 0xca 2c: 0c 94 65 00 jmp 0xca 30: 0c 94 65 00 jmp 0xca 34: 0c 94 65 00 jmp 0xca 38: 0c 94 65 00 jmp 0xca 3c: 0c 94 65 00 jmp 0xca 40: 0c 94 65 00 jmp 0xca 44: 0c 94 65 00 jmp 0xca 48: 0c 94 65 00 jmp 0xca 4c: 0c 94 65 00 jmp 0xca 50: 0c 94 65 00 jmp 0xca 00000054 <__ctors_end>: 54: 4e 02 muls r20, r30 56: 96 02 muls r25, r22 58: 9e 02 muls r25, r30 5a: b7 02 muls r27, r23 5c: 0d 03 fmul r16, r21 5e: e4 02 muls r30, r20 60: 48 03 fmul r20, r16 62: 61 03 mulsu r22, r17 64: 85 03 fmuls r16, r21 66: b8 03 fmulsu r19, r16 68: e0 03 fmuls r22, r16 6a: 1c 04 cpc r1, r12 6c: 3e 04 cpc r3, r14 6e: 5f 04 cpc r5, r15 70: 78 04 cpc r7, r8 72: a0 04 cpc r10, r0 74: dd 04 cpc r13, r13 76: f6 04 cpc r15, r6 78: 27 05 cpc r18, r7 7a: 62 05 cpc r22, r2 7c: 74 05 cpc r23, r4 7e: 8d 05 cpc r24, r13 80: b7 05 cpc r27, r7 82: d7 05 cpc r29, r7 84: ff 05 cpc r31, r15 86: 16 06 cpc r1, r22 88: 2d 06 cpc r2, r29 8a: 46 06 cpc r4, r22 8c: 66 06 cpc r6, r22 8e: 82 06 cpc r8, r18 90: 95 06 cpc r9, r21 92: ab 06 cpc r10, r27 00000094 <__init>: 94: 11 24 eor r1, r1 96: 1f be out 0x3f, r1 ; 63 98: cf e5 ldi r28, 0x5F ; 95 9a: d4 e0 ldi r29, 0x04 ; 4 9c: de bf out 0x3e, r29 ; 62 9e: cd bf out 0x3d, r28 ; 61 000000a0 <__do_copy_data>: a0: 11 e0 ldi r17, 0x01 ; 1 a2: a0 e6 ldi r26, 0x60 ; 96 a4: b0 e0 ldi r27, 0x00 ; 0 a6: e6 e8 ldi r30, 0x86 ; 134 a8: ff e0 ldi r31, 0x0F ; 15 aa: 02 c0 rjmp .+4 ; 0xb0 000000ac <.do_copy_data_loop>: ac: 05 90 lpm r0, Z+ ae: 0d 92 st X+, r0 000000b0 <.do_copy_data_start>: b0: a8 3f cpi r26, 0xF8 ; 248 b2: b1 07 cpc r27, r17 b4: d9 f7 brne .-10 ; 0xac 000000b6 <__do_clear_bss>: b6: 11 e0 ldi r17, 0x01 ; 1 b8: a8 ef ldi r26, 0xF8 ; 248 ba: b1 e0 ldi r27, 0x01 ; 1 bc: 01 c0 rjmp .+2 ; 0xc0 000000be <.do_clear_bss_loop>: be: 1d 92 st X+, r1 000000c0 <.do_clear_bss_start>: c0: ad 3f cpi r26, 0xFD ; 253 c2: b1 07 cpc r27, r17 c4: e1 f7 brne .-8 ; 0xbe c6: 0c 94 f9 06 jmp 0xdf2 000000ca <__bad_interrupt>: ca: 0c 94 00 00 jmp 0x0 000000ce : { #if (Fosc != 16000000L) Error "This code assumes a 16 MHz clock." #endif if (cnt < 1) return; ce: 00 97 sbiw r24, 0x00 ; 0 d0: 79 f0 breq .+30 ; 0xf0 /* the above compiles to "sbiw R,0 breq L which takes 4 clocks */ asm volatile ( d2: 06 c0 rjmp .+12 ; 0xe0 000000d4 : ... 000000e0 : ... ec: 01 97 sbiw r24, 0x01 ; 1 ee: 91 f7 brne .-28 ; 0xd4 "\n\t" "rjmp L_dl2%=" "\n" /* skip 6 nops for this instruction and the ones above */ "L_dl1%=:" "\n\t" /* almost one microsecond worth of NOPs follows .. */ "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n" "L_dl2%=:" "\n\t" /* enter here to skip 6 of the nops */ "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "sbiw %0,1" "\n\t" /* 2-clock instruction */ "brne L_dl1%=" "\n\t" /* usually 2-clock instruction */ ::"w" (cnt)); } /* DelayUs */ f0: 08 95 ret f2: 08 95 ret 000000f4 : void DelayMs (unsigned int ms) { if (ms < 1) return; f4: 00 97 sbiw r24, 0x00 ; 0 f6: 31 f0 breq .+12 ; 0x104 000000f8 : { uint16_t cnt; asm volatile ( f8: e0 ea ldi r30, 0xA0 ; 160 fa: ff e0 ldi r31, 0x0F ; 15 000000fc : fc: 31 97 sbiw r30, 0x01 ; 1 fe: f1 f7 brne .-4 ; 0xfc 100: 01 97 sbiw r24, 0x01 ; 1 102: d1 f7 brne .-12 ; 0xf8 "\n" "L_dl1%=:" "\n\t" "ldi %A0,%2" "\n\t" /* set up inner loop count */ "ldi %B0,%3" "\n" "L_dl2%=:" "\n\t" /* start a two-instruction, 4-clock inner loop */ "sbiw %A0, 1" "\n\t" "brne L_dl2%=" "\n\t" "sbiw %1,1" "\n\t" /* count one millisecond */ "brne L_dl1%=" "\n\t" : "=&w" (cnt) : "w" (ms), "M" ((unsigned int)(Fosc/4000) & 0xFF), "M" ((unsigned int)(Fosc/4000) >> 8) ); } } /* DelayMs */ 104: 08 95 ret 00000106 : /**************************************************************** * getch * * Get one character from the serial link. ****************************************************************/ unsigned char getch (void) { while (! (UCSRA & (1 << RXC))) 106: 5f 9b sbis 0x0b, 7 ; 11 108: fe cf rjmp .-4 ; 0x106 ; return UDR; 10a: 8c b1 in r24, 0x0c ; 12 10c: 99 27 eor r25, r25 } /* getch */ 10e: 08 95 ret 00000110 : /**************************************************************** * putch * * Put one character onto the serial link. ****************************************************************/ void putch (char c) { while (! (UCSRA & (1 << UDRE))) 110: 5d 9b sbis 0x0b, 5 ; 11 112: fe cf rjmp .-4 ; 0x110 ; UDR = c; 114: 8c b9 out 0x0c, r24 ; 12 } /* putch */ 116: 08 95 ret 00000118 : /**************************************************************** * set_aid_bus_address * * A helper function to aid_bus_read() and aid_bus_write(). * * The relevant pins are configured as outputs by * aid_mainboard_init(). * * Returns SUCCESS or FAILURE based on the plausability of the given * address. ****************************************************************/ int set_aid_bus_address (unsigned char address) { if (address > 15) 118: 80 31 cpi r24, 0x10 ; 16 11a: 18 f0 brcs .+6 ; 0x122 return FAILURE; 11c: 81 e0 ldi r24, 0x01 ; 1 11e: 90 e0 ldi r25, 0x00 ; 0 AID_BUS_ADDR = (AID_BUS_ADDR & 0x0F) | (address << AID_BUS_ADDR0); return SUCCESS; } /* set_aid_bus_address */ 120: 08 95 ret 122: 28 b3 in r18, 0x18 ; 24 124: 2f 70 andi r18, 0x0F ; 15 126: 99 27 eor r25, r25 128: 34 e0 ldi r19, 0x04 ; 4 12a: 88 0f add r24, r24 12c: 99 1f adc r25, r25 12e: 3a 95 dec r19 130: e1 f7 brne .-8 ; 0x12a 132: 28 2b or r18, r24 134: 28 bb out 0x18, r18 ; 24 136: 80 e0 ldi r24, 0x00 ; 0 138: 90 e0 ldi r25, 0x00 ; 0 13a: 08 95 ret 13c: 08 95 ret 0000013e : /**************************************************************** * set_aid_bus_data * * A helper function to aid_bus_write(). * ****************************************************************/ void set_aid_bus_data (unsigned char data) { 13e: 98 2f mov r25, r24 AID_BUS_DATA_DDR = 0xFF; /* Make port C an output. */ 140: 8f ef ldi r24, 0xFF ; 255 142: 84 bb out 0x14, r24 ; 20 AID_BUS_DATA = data; 144: 95 bb out 0x15, r25 ; 21 } /* set_aid_bus_data */ 146: 08 95 ret 00000148 : /**************************************************************** * get_aid_bus_data * * A helper function to aid_bus_read(). * ****************************************************************/ unsigned char get_aid_bus_data (void) { AID_BUS_DATA_DDR = 0; /* Make port C an input. */ 148: 14 ba out 0x14, r1 ; 20 return AID_BUS_DATA; 14a: 85 b3 in r24, 0x15 ; 21 14c: 99 27 eor r25, r25 } /* get_aid_bus_data */ 14e: 08 95 ret 00000150 : /**************************************************************** * char aid_bus_read * * Error checking idea: we could define this function as type * int and use numbers outside the range of an unsigned char to * indicate error conditions (e.g. invalid address). The onus * would be on the caller to check if the return value indicates * an error conditions and if not, then cast to extract the * intended 8 bits. ****************************************************************/ unsigned char aid_bus_read (unsigned char address) { 150: cf 93 push r28 unsigned char data = 0; /* default value in case read fails */ 152: c0 e0 ldi r28, 0x00 ; 0 if (set_aid_bus_address(address) == SUCCESS) { 154: 0e 94 8c 00 call 0x118 158: 89 2b or r24, r25 15a: 49 f4 brne .+18 ; 0x16e AID_BUS_RW &= ~(1 << AID_BUS_R); /* assert the /read signal */ 15c: c0 98 cbi 0x18, 0 ; 24 DelayUs(1); /* Wait for the daughter card to respond before we grab the data. */ 15e: 81 e0 ldi r24, 0x01 ; 1 160: 90 e0 ldi r25, 0x00 ; 0 162: 0e 94 67 00 call 0xce data = get_aid_bus_data(); 166: 0e 94 a4 00 call 0x148 16a: c8 2f mov r28, r24 AID_BUS_RW |= (1 << AID_BUS_R); /* unassert the /read signal */ 16c: c0 9a sbi 0x18, 0 ; 24 } return data; 16e: 8c 2f mov r24, r28 170: 99 27 eor r25, r25 } /* aid_bus_read */ 172: cf 91 pop r28 174: 08 95 ret 00000176 : /**************************************************************** * aid_bus_write * * Returns SUCCESS or FAILURE based on the plausibility of the * given address. ****************************************************************/ int aid_bus_write (unsigned char address, unsigned char data) { 176: 1f 93 push r17 178: cf 93 push r28 17a: df 93 push r29 17c: 16 2f mov r17, r22 if (set_aid_bus_address(address) == SUCCESS) { 17e: 0e 94 8c 00 call 0x118 182: ec 01 movw r28, r24 184: 89 2b or r24, r25 186: 59 f4 brne .+22 ; 0x19e set_aid_bus_data(data); 188: 81 2f mov r24, r17 18a: 0e 94 9f 00 call 0x13e AID_BUS_RW &= ~(1 << AID_BUS_W); /* assert the /write signal */ 18e: c1 98 cbi 0x18, 1 ; 24 DelayUs(1); /* Give the daughter card time to grab the data. */ 190: 81 e0 ldi r24, 0x01 ; 1 192: 90 e0 ldi r25, 0x00 ; 0 194: 0e 94 67 00 call 0xce AID_BUS_RW |= (1 << AID_BUS_W); /* unassert the /write signal */ 198: c1 9a sbi 0x18, 1 ; 24 return SUCCESS; 19a: ce 01 movw r24, r28 19c: 02 c0 rjmp .+4 ; 0x1a2 } return FAILURE; 19e: 81 e0 ldi r24, 0x01 ; 1 1a0: 90 e0 ldi r25, 0x00 ; 0 } /* aid_bus_write */ 1a2: df 91 pop r29 1a4: cf 91 pop r28 1a6: 1f 91 pop r17 1a8: 08 95 ret 000001aa : /**************************************************************** * aid_pwm_init * * Initialisation of the PWM outputs. ****************************************************************/ void aid_pwm_init(void) { /* Timer/Counter 0 .. */ /* Fast PWM mode, Fosc/1024 */ /* frequency is Fosc / (Prescale * 256), Prescale in 1,8,64,256,1024 */ /* Duty cycle set by TCNT0 */ TCCR0 = (1 << WGM00) | (1 << WGM01) /* fast PWM mode */ 1aa: 99 e6 ldi r25, 0x69 ; 105 1ac: 93 bf out 0x33, r25 ; 51 | (2 << COM00) /* clear OC0 on compare match */ | (1 << CS00); /* frequency prescale = 1 */ /* page 83 */ DDRB |= (1 << DDB3); /* make OC0 pin an output */ 1ae: bb 9a sbi 0x17, 3 ; 23 OCR0 = 0; /* set duty cycle to 0 */ 1b0: 1c be out 0x3c, r1 ; 60 /* Timer/Counter 1 .. page 96 */ /* ICR1 can define TOP value, therefore PWM frequency */ /* TCCR1A, see page 109 */ TCCR1A = (2 << COM1A0) /* fast PWM mode channel A */ 1b2: 82 ea ldi r24, 0xA2 ; 162 1b4: 8f bd out 0x2f, r24 ; 47 | (2 << COM1B0) /* fast PWM mode channel B */ | (2 << WGM10); /* fast PWM mode freq. from ICR1 */ /* TCCR1B, see page 112 */ TCCR1B = (3 << WGM12) /* fast PWM mode freq. from ICR1 */ 1b6: 8d e1 ldi r24, 0x1D ; 29 1b8: 8e bd out 0x2e, r24 ; 46 | (5 << CS10); /* clock prescaled by 256 */ DDRD |= (1 << DDD5) | (1 << DDD4); /* make A and B pins output */ 1ba: 81 b3 in r24, 0x11 ; 17 1bc: 80 63 ori r24, 0x30 ; 48 1be: 81 bb out 0x11, r24 ; 17 OCR1AH = 0; 1c0: 1b bc out 0x2b, r1 ; 43 OCR1AL = 0; 1c2: 1a bc out 0x2a, r1 ; 42 OCR1BH = 0; 1c4: 19 bc out 0x29, r1 ; 41 OCR1BL = 0; 1c6: 18 bc out 0x28, r1 ; 40 /* Timer/Counter 2 .. */ /* Seems just like Timer/Counter 0 */ /* Fast PWM mode, Fosc/256 */ /* frequency is Fosc / (Prescale * 256), Prescale in 1,8,64,256,1024 */ /* Duty cycle set by TCNT2 */ TCCR2 = (1 << WGM20) | (1 << WGM21) /* fast PWM mode */ 1c8: 95 bd out 0x25, r25 ; 37 | (2 << COM20) /* clear OC0 on compare match */ | (1 << CS20); /* frequency divisor = 1 */ /* page 129 */ DDRD |= (1 << DDD7); /* make OC2 pin an output */ 1ca: 8f 9a sbi 0x11, 7 ; 17 OCR2 = 0; /* set duty cycle to 0 */ 1cc: 13 bc out 0x23, r1 ; 35 } /* aid_pwm_init */ 1ce: 08 95 ret 000001d0 : /**************************************************************** * set_pwm_duty_cycle * * Set the PWM duty cycle by writing to the CCPR1L register and * CCP1CON<5:4> bits. * * PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) * * If the PWM duty cycle value is longer than the PWM period, the CCP1 * pin will not be cleared. The two LSB of each duty cycle are in a * different register. These are set to zero in pwm_init and not * touched here. ****************************************************************/ int set_pwm_duty_cycle (unsigned char addr, unsigned int duty_cycle) { 1d0: cf 93 push r28 1d2: c8 2f mov r28, r24 if (addr > 3) 1d4: 84 30 cpi r24, 0x04 ; 4 1d6: 18 f0 brcs .+6 ; 0x1de return FAILURE; /* illegal PWM address */ 1d8: 81 e0 ldi r24, 0x01 ; 1 1da: 90 e0 ldi r25, 0x00 ; 0 1dc: 43 c0 rjmp .+134 ; 0x264 else if (addr == 0) /* fixed frequency PWM */ 1de: 88 23 and r24, r24 1e0: 41 f4 brne .+16 ; 0x1f2 OCR0 = (256 * duty_cycle) / 100; 1e2: 96 2f mov r25, r22 1e4: 88 27 eor r24, r24 1e6: 64 e6 ldi r22, 0x64 ; 100 1e8: 70 e0 ldi r23, 0x00 ; 0 1ea: 0e 94 45 07 call 0xe8a 1ee: 6c bf out 0x3c, r22 ; 60 1f0: 37 c0 rjmp .+110 ; 0x260 else if (addr == 3) /* fixed frequency PWM */ 1f2: 83 30 cpi r24, 0x03 ; 3 1f4: 41 f4 brne .+16 ; 0x206 OCR2 = (256 * duty_cycle) / 100; 1f6: 96 2f mov r25, r22 1f8: 88 27 eor r24, r24 1fa: 64 e6 ldi r22, 0x64 ; 100 1fc: 70 e0 ldi r23, 0x00 ; 0 1fe: 0e 94 45 07 call 0xe8a 202: 63 bd out 0x23, r22 ; 35 204: 2d c0 rjmp .+90 ; 0x260 else { unsigned int p; /* compute duty cycle as a percent of the PWM frequency count */ p = ICR1L; 206: 86 b5 in r24, 0x26 ; 38 208: e8 2f mov r30, r24 20a: ff 27 eor r31, r31 p = p | (ICR1H << 8); 20c: 87 b5 in r24, 0x27 ; 39 20e: 99 27 eor r25, r25 210: 98 2f mov r25, r24 212: 88 27 eor r24, r24 214: e8 2b or r30, r24 216: f9 2b or r31, r25 p = (p * (long)duty_cycle) / 100; 218: cf 01 movw r24, r30 21a: aa 27 eor r26, r26 21c: bb 27 eor r27, r27 21e: 9b 01 movw r18, r22 220: 44 27 eor r20, r20 222: 55 27 eor r21, r21 224: bc 01 movw r22, r24 226: cd 01 movw r24, r26 228: 0e 94 26 07 call 0xe4c 22c: dc 01 movw r26, r24 22e: cb 01 movw r24, r22 230: bc 01 movw r22, r24 232: cd 01 movw r24, r26 234: 24 e6 ldi r18, 0x64 ; 100 236: 30 e0 ldi r19, 0x00 ; 0 238: 40 e0 ldi r20, 0x00 ; 0 23a: 50 e0 ldi r21, 0x00 ; 0 23c: 0e 94 6c 07 call 0xed8 240: da 01 movw r26, r20 242: c9 01 movw r24, r18 244: f9 01 movw r30, r18 if (addr == 1) { 246: c1 30 cpi r28, 0x01 ; 1 248: 29 f4 brne .+10 ; 0x254 OCR1AH = p >> 8; 24a: 89 2f mov r24, r25 24c: 99 27 eor r25, r25 24e: 8b bd out 0x2b, r24 ; 43 OCR1AL = (unsigned char)p; 250: ea bd out 0x2a, r30 ; 42 252: 06 c0 rjmp .+12 ; 0x260 } else if (addr == 2) { 254: c2 30 cpi r28, 0x02 ; 2 256: 21 f4 brne .+8 ; 0x260 OCR1BH = p >> 8; 258: 89 2f mov r24, r25 25a: 99 27 eor r25, r25 25c: 89 bd out 0x29, r24 ; 41 OCR1BL = (unsigned char)p; 25e: e8 bd out 0x28, r30 ; 40 } } return SUCCESS; 260: 80 e0 ldi r24, 0x00 ; 0 262: 90 e0 ldi r25, 0x00 ; 0 } /* set_pwm_duty_cycle */ 264: cf 91 pop r28 266: 08 95 ret 00000268 : /**************************************************************** * set_pwm_frequency * * The argument is used to set the Timer 2 period. * * TODO: What units should freq have? Hz? kHz? * * Both PWM pins use the same timer and therefore have the same frequency. * Set the PWM period by writing to the PR2 register. * * PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) * 1/f = [(PR2) + 1] * 4 * FOSC/4 * (1) * 1/f = [(PR2) + 1] * FOSC * (1) * 1/f = [(PR2) + 1] * FOSC * [PR2 + 1] = 1/(f * FOSC) * PR2 = 1/(f * FOSC) - 1 * * The PR2 register is 8 bits wide. ****************************************************************/ void set_pwm_frequency (unsigned int freq) { 268: 9c 01 movw r18, r24 /* Temporary, this whole if statment should be replaced with a * calculation of PR2 from freq * * Here's what we'd really like to do: PR2 = 1/(freq*FOSC) - 1; */ /* probably stop PWM First, so as not to skip a compare match */ ICR1H = freq >> 8; 26a: 83 2f mov r24, r19 26c: 99 27 eor r25, r25 26e: 87 bd out 0x27, r24 ; 39 ICR1L = (unsigned char)freq; 270: 26 bd out 0x26, r18 ; 38 } /* set_pwm_frequency */ 272: 08 95 ret 00000274 : /**************************************************************** * set_pwm * * Set the frequency and duty cycles of both PWM outputs at once. ****************************************************************/ void set_pwm(unsigned int freq, unsigned int dc1, unsigned int dc2) { 274: ef 92 push r14 276: ff 92 push r15 278: 0f 93 push r16 27a: 1f 93 push r17 27c: 8b 01 movw r16, r22 27e: 7a 01 movw r14, r20 set_pwm_frequency(freq); 280: 0e 94 34 01 call 0x268 set_pwm_duty_cycle(1, dc1); 284: b8 01 movw r22, r16 286: 81 e0 ldi r24, 0x01 ; 1 288: 0e 94 e8 00 call 0x1d0 set_pwm_duty_cycle(2, dc2); 28c: b7 01 movw r22, r14 28e: 82 e0 ldi r24, 0x02 ; 2 290: 0e 94 e8 00 call 0x1d0 } /* set_pwm */ 294: 1f 91 pop r17 296: 0f 91 pop r16 298: ff 90 pop r15 29a: ef 90 pop r14 29c: 08 95 ret 0000029e : /**************************************************************** * get_ad * * Handler function for the "aA" command. Initiates an analog to * digital conversion, wait for it to complete, and returns the result * over the serial port. ****************************************************************/ unsigned int get_ad (unsigned char address) { 29e: 98 2f mov r25, r24 unsigned int result; ADCSRA = (1 << ADEN) /* switch on the ADC converter */ 2a0: 87 e9 ldi r24, 0x97 ; 151 2a2: 86 b9 out 0x06, r24 ; 6 | (1 << ADIF) /* ensure interrupt flag is clear */ | (0 << ADIE) /* ensure interrupt is disabled */ | (7 << ADPS0) /* prescale I/O Clock by 128 for ADC clock */ ; ADMUX = (0 << ADLAR) /* right-adjust ADC result */ 2a4: 97 70 andi r25, 0x07 ; 7 2a6: 90 64 ori r25, 0x40 ; 64 2a8: 97 b9 out 0x07, r25 ; 7 | (1 << REFS0) /* use AVcc as reference */ | (address & 7) /* ADC channel address */ ; /* 3. Wait the required acquisition time. */ /*DelayMs (10);*/ /* 4. Start conversion */ ADCSRA |= (1 << ADSC); 2aa: 36 9a sbi 0x06, 6 ; 6 /* 5. Wait for A/D conversion to complete, */ while (ADCSRA & (1 << ADSC)) 2ac: 36 99 sbic 0x06, 6 ; 6 2ae: fe cf rjmp .-4 ; 0x2ac ; /* wait */ /* 6. Read A/D result register pair . */ result = ADCL; 2b0: 84 b1 in r24, 0x04 ; 4 2b2: 28 2f mov r18, r24 2b4: 33 27 eor r19, r19 result |= ADCH << 8; 2b6: 85 b1 in r24, 0x05 ; 5 2b8: 99 27 eor r25, r25 2ba: 98 2f mov r25, r24 2bc: 88 27 eor r24, r24 2be: 28 2b or r18, r24 2c0: 39 2b or r19, r25 ADCSRA |= (1 << ADIF); /* Turn off the interrupt flag. */ 2c2: 34 9a sbi 0x06, 4 ; 6 ADCSRA &= ~(1 << ADEN); /* turn off the ADC to conserve batteries */ 2c4: 37 98 cbi 0x06, 7 ; 6 return result; } /* get_ad */ 2c6: c9 01 movw r24, r18 2c8: 08 95 ret 000002ca : /**************************************************************** * aid_serial_init * ****************************************************************/ void aid_serial_init(void) { UCSRA &= ~(1 << U2X); /* disable "extra speed" switch */ 2ca: 59 98 cbi 0x0b, 1 ; 11 UBRRH = ((long)Fosc / (16 * 19200L) - 1) >> 8; /* 19200 baud */ 2cc: 10 bc out 0x20, r1 ; 32 UBRRL = ((long)Fosc / (16 * 19200L) - 1) & 0xFF; /* 19200 baud */ 2ce: 83 e3 ldi r24, 0x33 ; 51 2d0: 89 b9 out 0x09, r24 ; 9 UCSRC = (1 << URSEL) | (0 << USBS) | (3 << UCSZ0); /* framing 8N1 */ 2d2: 86 e8 ldi r24, 0x86 ; 134 2d4: 80 bd out 0x20, r24 ; 32 UCSRB = (1 << RXEN) | (1 << TXEN); /* enable receive and send */ 2d6: 88 e1 ldi r24, 0x18 ; 24 2d8: 8a b9 out 0x0a, r24 ; 10 } /* aid_serial_init */ 2da: 08 95 ret 000002dc : /**************************************************************** * aid_bus_init * ****************************************************************/ void aid_bus_init(void) { /* Initialise the /R and /W pins to logic high... */ AID_BUS_RW |= (1<: /**************************************************************** * aid_mainboard_init * * Main board initialisation routine. Call this first in main.c ****************************************************************/ void aid_mainboard_init(void) { /* "Flash fuse" bits control clock generation... CKSEL = 7 << CKSEL0 # this value selects crystal, high speed */ /* Configure all 8 A/D lines to be inputs. */ AID_ADC_DDR = 0; 2f2: 1a ba out 0x1a, r1 ; 26 /* Call some other initialization routines. */ aid_bus_init(); 2f4: 0e 94 6e 01 call 0x2dc aid_serial_init(); 2f8: 0e 94 65 01 call 0x2ca aid_pwm_init(); 2fc: 0e 94 d5 00 call 0x1aa /* do other useful things here */ } /* aid_mainboard_init */ 300: 08 95 ret 00000302 : * * Put a null-terminated string of characters onto the serial link. ****************************************************************/ int puts (const char *s) { 302: cf 93 push r28 304: df 93 push r29 306: ec 01 movw r28, r24 while (*s != 0) 308: 88 81 ld r24, Y 30a: 88 23 and r24, r24 30c: 31 f0 breq .+12 ; 0x31a putch (*s++); 30e: 89 91 ld r24, Y+ 310: 0e 94 88 00 call 0x110 314: 88 81 ld r24, Y 316: 88 23 and r24, r24 318: d1 f7 brne .-12 ; 0x30e return 0; } /* puts */ 31a: 80 e0 ldi r24, 0x00 ; 0 31c: 90 e0 ldi r25, 0x00 ; 0 31e: df 91 pop r29 320: cf 91 pop r28 322: 08 95 ret 00000324 : /**************************************************************** * put3digits * * Type "unsigned char" has a range of [0,255] so any value can be * displayed by 3 decimal digits or less. * ****************************************************************/ void put3digits (unsigned char num) { 324: af 92 push r10 326: bf 92 push r11 328: cf 92 push r12 32a: df 92 push r13 32c: ef 92 push r14 32e: ff 92 push r15 330: 0f 93 push r16 332: 1f 93 push r17 div_t h = div (num, 100); 334: 99 27 eor r25, r25 336: 64 e6 ldi r22, 0x64 ; 100 338: 70 e0 ldi r23, 0x00 ; 0 33a: 0e 94 59 07 call 0xeb2 33e: 7b 01 movw r14, r22 340: 8c 01 movw r16, r24 div_t t = div (h.rem, 10); 342: 6a e0 ldi r22, 0x0A ; 10 344: 70 e0 ldi r23, 0x00 ; 0 346: c8 01 movw r24, r16 348: 0e 94 59 07 call 0xeb2 34c: 5b 01 movw r10, r22 34e: 6c 01 movw r12, r24 if (h.quot) { 350: e1 14 cp r14, r1 352: f1 04 cpc r15, r1 354: 29 f0 breq .+10 ; 0x360 putch ('0' + h.quot); 356: 8e 2d mov r24, r14 358: 80 5d subi r24, 0xD0 ; 208 35a: 0e 94 88 00 call 0x110 putch ('0' + t.quot); 35e: 02 c0 rjmp .+4 ; 0x364 } else if (t.quot) 360: 67 2b or r22, r23 362: 21 f0 breq .+8 ; 0x36c putch ('0' + t.quot); 364: 8a 2d mov r24, r10 366: 80 5d subi r24, 0xD0 ; 208 368: 0e 94 88 00 call 0x110 putch ('0' + t.rem); 36c: 8c 2d mov r24, r12 36e: 80 5d subi r24, 0xD0 ; 208 370: 0e 94 88 00 call 0x110 } /* put3digits */ 374: 1f 91 pop r17 376: 0f 91 pop r16 378: ff 90 pop r15 37a: ef 90 pop r14 37c: df 90 pop r13 37e: cf 90 pop r12 380: bf 90 pop r11 382: af 90 pop r10 384: 08 95 ret 00000386 : /**************************************************************** * put_some_digits ****************************************************************/ void put_some_digits (unsigned int num) { 386: bf 92 push r11 388: cf 92 push r12 38a: df 92 push r13 38c: ef 92 push r14 38e: ff 92 push r15 390: 0f 93 push r16 392: 1f 93 push r17 394: cf 93 push r28 396: df 93 push r29 /*True once we're past the first non-zero digit. ("past leading zeros")*/ unsigned char plz = 0; 398: bb 24 eor r11, r11 /* Order of magnitude of the current digit. */ static const unsigned int mag [4] = {10000,1000,100,10}; div_t D; int i; if (!num) { 39a: 00 97 sbiw r24, 0x00 ; 0 39c: 11 f4 brne .+4 ; 0x3a2 putch('0'); 39e: 80 e3 ldi r24, 0x30 ; 48 3a0: 1f c0 rjmp .+62 ; 0x3e0 return; } D.rem = num; 3a2: 8c 01 movw r16, r24 for (i=0; i < 4; ++i) { 3a4: c8 ed ldi r28, 0xD8 ; 216 3a6: d1 e0 ldi r29, 0x01 ; 1 3a8: 66 e0 ldi r22, 0x06 ; 6 3aa: c6 2e mov r12, r22 3ac: d1 2c mov r13, r1 3ae: cc 0e add r12, r28 3b0: dd 1e adc r13, r29 D = div (D.rem, mag[i]); 3b2: 68 81 ld r22, Y 3b4: 79 81 ldd r23, Y+1 ; 0x01 3b6: c8 01 movw r24, r16 3b8: 0e 94 59 07 call 0xeb2 3bc: 7b 01 movw r14, r22 3be: 8c 01 movw r16, r24 if (D.quot || plz) { 3c0: 67 2b or r22, r23 3c2: 11 f4 brne .+4 ; 0x3c8 3c4: bb 20 and r11, r11 3c6: 31 f0 breq .+12 ; 0x3d4 putch ('0' + D.quot); 3c8: 8e 2d mov r24, r14 3ca: 80 5d subi r24, 0xD0 ; 208 3cc: 0e 94 88 00 call 0x110 plz = 1; 3d0: 51 e0 ldi r21, 0x01 ; 1 3d2: b5 2e mov r11, r21 3d4: 22 96 adiw r28, 0x02 ; 2 3d6: cc 16 cp r12, r28 3d8: dd 06 cpc r13, r29 3da: 5c f7 brge .-42 ; 0x3b2 } } putch ('0' + D.rem); 3dc: 80 2f mov r24, r16 3de: 80 5d subi r24, 0xD0 ; 208 3e0: 0e 94 88 00 call 0x110 } /* put_some_digits */ 3e4: df 91 pop r29 3e6: cf 91 pop r28 3e8: 1f 91 pop r17 3ea: 0f 91 pop r16 3ec: ff 90 pop r15 3ee: ef 90 pop r14 3f0: df 90 pop r13 3f2: cf 90 pop r12 3f4: bf 90 pop r11 3f6: 08 95 ret 000003f8 : /* Emit a greeting, then restart the command processor by * setting state to INIT. */ void aid_cmd_restart(void) { puts(prompt); 3f8: 82 ed ldi r24, 0xD2 ; 210 3fa: 91 e0 ldi r25, 0x01 ; 1 3fc: 0e 94 81 01 call 0x302 puts(eol); 400: 8b ea ldi r24, 0xAB ; 171 402: 91 e0 ldi r25, 0x01 ; 1 404: 0e 94 81 01 call 0x302 cmd_state = INIT; 408: 10 92 f9 01 sts 0x01F9, r1 40c: 10 92 f8 01 sts 0x01F8, r1 return; } 410: 08 95 ret 00000412 : /* Emit an acknowledgement message then go back to state INIT. */ void ack_then_INIT(void) { puts(eol); 412: 8b ea ldi r24, 0xAB ; 171 414: 91 e0 ldi r25, 0x01 ; 1 416: 0e 94 81 01 call 0x302 puts(ack); 41a: 84 ea ldi r24, 0xA4 ; 164 41c: 91 e0 ldi r25, 0x01 ; 1 41e: 0e 94 81 01 call 0x302 puts(eol); 422: 8b ea ldi r24, 0xAB ; 171 424: 91 e0 ldi r25, 0x01 ; 1 426: 0e 94 81 01 call 0x302 cmd_state = INIT; 42a: 10 92 f9 01 sts 0x01F9, r1 42e: 10 92 f8 01 sts 0x01F8, r1 return; } 432: 08 95 ret 00000434 : /* Emit an error message then go back to state INIT. */ void err_then_INIT(void) { puts(eol); 434: 8b ea ldi r24, 0xAB ; 171 436: 91 e0 ldi r25, 0x01 ; 1 438: 0e 94 81 01 call 0x302 puts(err); 43c: 87 ea ldi r24, 0xA7 ; 167 43e: 91 e0 ldi r25, 0x01 ; 1 440: 0e 94 81 01 call 0x302 puts(eol); 444: 8b ea ldi r24, 0xAB ; 171 446: 91 e0 ldi r25, 0x01 ; 1 448: 0e 94 81 01 call 0x302 cmd_state = INIT; 44c: 10 92 f9 01 sts 0x01F9, r1 450: 10 92 f8 01 sts 0x01F8, r1 return; } 454: 08 95 ret 00000456 : void cmd_next_char(unsigned char inchar) { 456: 0f 93 push r16 458: 1f 93 push r17 45a: cf 93 push r28 45c: c8 2f mov r28, r24 if (isalpha(inchar)) 45e: 08 2f mov r16, r24 460: 11 27 eor r17, r17 462: c8 01 movw r24, r16 464: 0e 94 ab 07 call 0xf56 468: 89 2b or r24, r25 46a: 21 f0 breq .+8 ; 0x474 { inchar = tolower(inchar); 46c: c8 01 movw r24, r16 46e: 0e 94 ba 07 call 0xf74 472: c8 2f mov r28, r24 } switch (cmd_state) 474: 80 91 f8 01 lds r24, 0x01F8 478: 90 91 f9 01 lds r25, 0x01F9 47c: aa 27 eor r26, r26 47e: 97 fd sbrc r25, 7 480: a0 95 com r26 482: ba 2f mov r27, r26 484: fc 01 movw r30, r24 486: 80 97 sbiw r24, 0x20 ; 32 488: 08 f0 brcs .+2 ; 0x48c 48a: af c4 rjmp .+2398 ; 0xdea 48c: e6 5d subi r30, 0xD6 ; 214 48e: ff 4f sbci r31, 0xFF ; 255 490: ee 0f add r30, r30 492: ff 1f adc r31, r31 494: 05 90 lpm r0, Z+ 496: f4 91 lpm r31, Z 498: e0 2d mov r30, r0 49a: 09 94 ijmp { case INIT: if (inchar=='r') 49c: c2 37 cpi r28, 0x72 ; 114 49e: 39 f4 brne .+14 ; 0x4ae { cmd_state = R; 4a0: 82 e0 ldi r24, 0x02 ; 2 4a2: 90 e0 ldi r25, 0x00 ; 0 4a4: 90 93 f9 01 sts 0x01F9, r25 4a8: 80 93 f8 01 sts 0x01F8, r24 4ac: 9e c4 rjmp .+2364 ; 0xdea } else if (inchar=='w') 4ae: c7 37 cpi r28, 0x77 ; 119 4b0: 39 f4 brne .+14 ; 0x4c0 { cmd_state = W; 4b2: 86 e0 ldi r24, 0x06 ; 6 4b4: 90 e0 ldi r25, 0x00 ; 0 4b6: 90 93 f9 01 sts 0x01F9, r25 4ba: 80 93 f8 01 sts 0x01F8, r24 4be: 95 c4 rjmp .+2346 ; 0xdea } else if (inchar=='p') 4c0: c0 37 cpi r28, 0x70 ; 112 4c2: 39 f4 brne .+14 ; 0x4d2 { cmd_state = P; 4c4: 8b e0 ldi r24, 0x0B ; 11 4c6: 90 e0 ldi r25, 0x00 ; 0 4c8: 90 93 f9 01 sts 0x01F9, r25 4cc: 80 93 f8 01 sts 0x01F8, r24 4d0: 8c c4 rjmp .+2328 ; 0xdea } else if (inchar=='a') 4d2: c1 36 cpi r28, 0x61 ; 97 4d4: 39 f4 brne .+14 ; 0x4e4 { cmd_state = A; 4d6: 84 e1 ldi r24, 0x14 ; 20 4d8: 90 e0 ldi r25, 0x00 ; 0 4da: 90 93 f9 01 sts 0x01F9, r25 4de: 80 93 f8 01 sts 0x01F8, r24 4e2: 83 c4 rjmp .+2310 ; 0xdea } else if (inchar=='e') 4e4: c5 36 cpi r28, 0x65 ; 101 4e6: 39 f4 brne .+14 ; 0x4f6 { cmd_state = E; 4e8: 88 e1 ldi r24, 0x18 ; 24 4ea: 90 e0 ldi r25, 0x00 ; 0 4ec: 90 93 f9 01 sts 0x01F9, r25 4f0: 80 93 f8 01 sts 0x01F8, r24 4f4: 7a c4 rjmp .+2292 ; 0xdea } else if (inchar=='h') 4f6: c8 36 cpi r28, 0x68 ; 104 4f8: 39 f4 brne .+14 ; 0x508 { cmd_state = H; 4fa: 8f e1 ldi r24, 0x1F ; 31 4fc: 90 e0 ldi r25, 0x00 ; 0 4fe: 90 93 f9 01 sts 0x01F9, r25 502: 80 93 f8 01 sts 0x01F8, r24 506: 71 c4 rjmp .+2274 ; 0xdea } /* else if (inchar=='m') { cmd_state = M; } */ else if (isEOLchar(inchar)) 508: ca 30 cpi r28, 0x0A ; 10 50a: 19 f0 breq .+6 ; 0x512 50c: cd 30 cpi r28, 0x0D ; 13 50e: 09 f0 breq .+2 ; 0x512 510: 6c c4 rjmp .+2264 ; 0xdea { /* Blank line? We didn't get a command so print the * error message and stay in state INIT. */ puts(eol); 512: 8b ea ldi r24, 0xAB ; 171 514: 91 e0 ldi r25, 0x01 ; 1 516: 0e 94 81 01 call 0x302 puts(err); 51a: 87 ea ldi r24, 0xA7 ; 167 51c: 91 e0 ldi r25, 0x01 ; 1 51e: 0e 94 81 01 call 0x302 puts(eol); 522: 8b ea ldi r24, 0xAB ; 171 524: 91 e0 ldi r25, 0x01 ; 1 526: 0e 94 81 01 call 0x302 } break; 52a: 5f c4 rjmp .+2238 ; 0xdea case ERROR: if (isEOLchar(inchar)) 52c: ca 30 cpi r28, 0x0A ; 10 52e: 19 f0 breq .+6 ; 0x536 530: cd 30 cpi r28, 0x0D ; 13 532: 09 f0 breq .+2 ; 0x536 534: 5a c4 rjmp .+2228 ; 0xdea { err_then_INIT(); 536: 0e 94 1a 02 call 0x434 } /* Else stay here and keep eating characters. */ break; 53a: 57 c4 rjmp .+2222 ; 0xdea case R: if (isWSchar(inchar)) 53c: c0 32 cpi r28, 0x20 ; 32 53e: 11 f0 breq .+4 ; 0x544 540: c9 30 cpi r28, 0x09 ; 9 542: 39 f4 brne .+14 ; 0x552 { cmd_state = R_; 544: 83 e0 ldi r24, 0x03 ; 3 546: 90 e0 ldi r25, 0x00 ; 0 548: 90 93 f9 01 sts 0x01F9, r25 54c: 80 93 f8 01 sts 0x01F8, r24 550: 4c c4 rjmp .+2200 ; 0xdea } else if (isEOLchar(inchar)) 552: ca 30 cpi r28, 0x0A ; 10 554: 11 f0 breq .+4 ; 0x55a 556: cd 30 cpi r28, 0x0D ; 13 558: 19 f4 brne .+6 ; 0x560 { err_then_INIT(); 55a: 0e 94 1a 02 call 0x434 55e: 45 c4 rjmp .+2186 ; 0xdea } else { cmd_state = ERROR; 560: 81 e0 ldi r24, 0x01 ; 1 562: 90 e0 ldi r25, 0x00 ; 0 564: 90 93 f9 01 sts 0x01F9, r25 568: 80 93 f8 01 sts 0x01F8, r24 } break; 56c: 3e c4 rjmp .+2172 ; 0xdea case R_: if (isdigit(inchar)) 56e: 8c 2f mov r24, r28 570: 99 27 eor r25, r25 572: 0e 94 b3 07 call 0xf66 576: 89 2b or r24, r25 578: 51 f0 breq .+20 ; 0x58e { addr = inchar - '0'; 57a: c0 53 subi r28, 0x30 ; 48 57c: c0 93 fa 01 sts 0x01FA, r28 cmd_state = R_A; 580: 84 e0 ldi r24, 0x04 ; 4 582: 90 e0 ldi r25, 0x00 ; 0 584: 90 93 f9 01 sts 0x01F9, r25 588: 80 93 f8 01 sts 0x01F8, r24 58c: 2e c4 rjmp .+2140 ; 0xdea } else if (inchar=='*') 58e: ca 32 cpi r28, 0x2A ; 42 590: 39 f4 brne .+14 ; 0x5a0 { cmd_state = R_all; 592: 85 e0 ldi r24, 0x05 ; 5 594: 90 e0 ldi r25, 0x00 ; 0 596: 90 93 f9 01 sts 0x01F9, r25 59a: 80 93 f8 01 sts 0x01F8, r24 59e: 25 c4 rjmp .+2122 ; 0xdea } else if (isWSchar(inchar)) 5a0: c0 32 cpi r28, 0x20 ; 32 5a2: 09 f4 brne .+2 ; 0x5a6 5a4: 22 c4 rjmp .+2116 ; 0xdea 5a6: c9 30 cpi r28, 0x09 ; 9 5a8: 09 f4 brne .+2 ; 0x5ac 5aa: 1f c4 rjmp .+2110 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) 5ac: ca 30 cpi r28, 0x0A ; 10 5ae: 11 f0 breq .+4 ; 0x5b4 5b0: cd 30 cpi r28, 0x0D ; 13 5b2: 19 f4 brne .+6 ; 0x5ba { err_then_INIT(); 5b4: 0e 94 1a 02 call 0x434 5b8: 18 c4 rjmp .+2096 ; 0xdea } else { cmd_state = ERROR; 5ba: 81 e0 ldi r24, 0x01 ; 1 5bc: 90 e0 ldi r25, 0x00 ; 0 5be: 90 93 f9 01 sts 0x01F9, r25 5c2: 80 93 f8 01 sts 0x01F8, r24 } break; 5c6: 11 c4 rjmp .+2082 ; 0xdea case R_all: if (isEOLchar(inchar)) 5c8: ca 30 cpi r28, 0x0A ; 10 5ca: 11 f0 breq .+4 ; 0x5d0 5cc: cd 30 cpi r28, 0x0D ; 13 5ce: f1 f4 brne .+60 ; 0x60c { puts(eol); 5d0: 8b ea ldi r24, 0xAB ; 171 5d2: 91 e0 ldi r25, 0x01 ; 1 5d4: 0e 94 81 01 call 0x302 for (addr=0; addr<=15; addr++) 5d8: 10 92 fa 01 sts 0x01FA, r1 { data = aid_bus_read(addr); 5dc: 80 91 fa 01 lds r24, 0x01FA 5e0: 0e 94 a8 00 call 0x150 5e4: 99 27 eor r25, r25 5e6: 90 93 fc 01 sts 0x01FC, r25 5ea: 80 93 fb 01 sts 0x01FB, r24 put_some_digits(data); 5ee: 0e 94 c3 01 call 0x386 putch(' '); 5f2: 80 e2 ldi r24, 0x20 ; 32 5f4: 0e 94 88 00 call 0x110 5f8: 80 91 fa 01 lds r24, 0x01FA 5fc: 8f 5f subi r24, 0xFF ; 255 5fe: 80 93 fa 01 sts 0x01FA, r24 602: 80 31 cpi r24, 0x10 ; 16 604: 58 f3 brcs .-42 ; 0x5dc } ack_then_INIT(); 606: 0e 94 09 02 call 0x412 60a: ef c3 rjmp .+2014 ; 0xdea } else { cmd_state = ERROR; 60c: 81 e0 ldi r24, 0x01 ; 1 60e: 90 e0 ldi r25, 0x00 ; 0 610: 90 93 f9 01 sts 0x01F9, r25 614: 80 93 f8 01 sts 0x01F8, r24 } break; 618: e8 c3 rjmp .+2000 ; 0xdea case R_A: if (isEOLchar(inchar)) 61a: ca 30 cpi r28, 0x0A ; 10 61c: 11 f0 breq .+4 ; 0x622 61e: cd 30 cpi r28, 0x0D ; 13 620: b1 f4 brne .+44 ; 0x64e { data = aid_bus_read(addr); 622: 80 91 fa 01 lds r24, 0x01FA 626: 0e 94 a8 00 call 0x150 62a: 99 27 eor r25, r25 62c: 90 93 fc 01 sts 0x01FC, r25 630: 80 93 fb 01 sts 0x01FB, r24 puts(eol); 634: 8b ea ldi r24, 0xAB ; 171 636: 91 e0 ldi r25, 0x01 ; 1 638: 0e 94 81 01 call 0x302 put_some_digits(data); 63c: 80 91 fb 01 lds r24, 0x01FB 640: 90 91 fc 01 lds r25, 0x01FC 644: 0e 94 c3 01 call 0x386 ack_then_INIT(); 648: 0e 94 09 02 call 0x412 64c: ce c3 rjmp .+1948 ; 0xdea } else if (isdigit(inchar)) 64e: 8c 2f mov r24, r28 650: 99 27 eor r25, r25 652: 0e 94 b3 07 call 0xf66 656: 89 2b or r24, r25 658: a1 f0 breq .+40 ; 0x682 { addr *= 10; 65a: 90 91 fa 01 lds r25, 0x01FA addr += (inchar - '0'); 65e: 8a e0 ldi r24, 0x0A ; 10 660: 98 9f mul r25, r24 662: 80 2d mov r24, r0 664: 11 24 eor r1, r1 666: 8c 0f add r24, r28 668: 80 53 subi r24, 0x30 ; 48 66a: 80 93 fa 01 sts 0x01FA, r24 if (addr > MAX_AID_BUS_ADDRESS) 66e: 80 31 cpi r24, 0x10 ; 16 670: 08 f4 brcc .+2 ; 0x674 672: bb c3 rjmp .+1910 ; 0xdea { cmd_state = ERROR; 674: 81 e0 ldi r24, 0x01 ; 1 676: 90 e0 ldi r25, 0x00 ; 0 678: 90 93 f9 01 sts 0x01F9, r25 67c: 80 93 f8 01 sts 0x01F8, r24 680: b4 c3 rjmp .+1896 ; 0xdea } } else { cmd_state = ERROR; 682: 81 e0 ldi r24, 0x01 ; 1 684: 90 e0 ldi r25, 0x00 ; 0 686: 90 93 f9 01 sts 0x01F9, r25 68a: 80 93 f8 01 sts 0x01F8, r24 } break; 68e: ad c3 rjmp .+1882 ; 0xdea case W: if (isWSchar(inchar)) 690: c0 32 cpi r28, 0x20 ; 32 692: 11 f0 breq .+4 ; 0x698 694: c9 30 cpi r28, 0x09 ; 9 696: 39 f4 brne .+14 ; 0x6a6 { cmd_state = W_; 698: 87 e0 ldi r24, 0x07 ; 7 69a: 90 e0 ldi r25, 0x00 ; 0 69c: 90 93 f9 01 sts 0x01F9, r25 6a0: 80 93 f8 01 sts 0x01F8, r24 6a4: a2 c3 rjmp .+1860 ; 0xdea } else if (isEOLchar(inchar)) 6a6: ca 30 cpi r28, 0x0A ; 10 6a8: 11 f0 breq .+4 ; 0x6ae 6aa: cd 30 cpi r28, 0x0D ; 13 6ac: 19 f4 brne .+6 ; 0x6b4 { err_then_INIT(); 6ae: 0e 94 1a 02 call 0x434 6b2: 9b c3 rjmp .+1846 ; 0xdea } else { cmd_state = ERROR; 6b4: 81 e0 ldi r24, 0x01 ; 1 6b6: 90 e0 ldi r25, 0x00 ; 0 6b8: 90 93 f9 01 sts 0x01F9, r25 6bc: 80 93 f8 01 sts 0x01F8, r24 } break; 6c0: 94 c3 rjmp .+1832 ; 0xdea case W_: if (isdigit(inchar)) 6c2: 8c 2f mov r24, r28 6c4: 99 27 eor r25, r25 6c6: 0e 94 b3 07 call 0xf66 6ca: 89 2b or r24, r25 6cc: 51 f0 breq .+20 ; 0x6e2 { addr = inchar - '0'; 6ce: c0 53 subi r28, 0x30 ; 48 6d0: c0 93 fa 01 sts 0x01FA, r28 cmd_state = W_A; 6d4: 88 e0 ldi r24, 0x08 ; 8 6d6: 90 e0 ldi r25, 0x00 ; 0 6d8: 90 93 f9 01 sts 0x01F9, r25 6dc: 80 93 f8 01 sts 0x01F8, r24 6e0: 84 c3 rjmp .+1800 ; 0xdea } else if (isWSchar(inchar)) 6e2: c0 32 cpi r28, 0x20 ; 32 6e4: 09 f4 brne .+2 ; 0x6e8 6e6: 81 c3 rjmp .+1794 ; 0xdea 6e8: c9 30 cpi r28, 0x09 ; 9 6ea: 09 f4 brne .+2 ; 0x6ee 6ec: 7e c3 rjmp .+1788 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) 6ee: ca 30 cpi r28, 0x0A ; 10 6f0: 11 f0 breq .+4 ; 0x6f6 6f2: cd 30 cpi r28, 0x0D ; 13 6f4: 19 f4 brne .+6 ; 0x6fc { err_then_INIT(); 6f6: 0e 94 1a 02 call 0x434 6fa: 77 c3 rjmp .+1774 ; 0xdea } else { cmd_state = ERROR; 6fc: 81 e0 ldi r24, 0x01 ; 1 6fe: 90 e0 ldi r25, 0x00 ; 0 700: 90 93 f9 01 sts 0x01F9, r25 704: 80 93 f8 01 sts 0x01F8, r24 } break; 708: 70 c3 rjmp .+1760 ; 0xdea case W_A: if (isWSchar(inchar)) 70a: c0 32 cpi r28, 0x20 ; 32 70c: 11 f0 breq .+4 ; 0x712 70e: c9 30 cpi r28, 0x09 ; 9 710: 39 f4 brne .+14 ; 0x720 { cmd_state = W_A_; 712: 89 e0 ldi r24, 0x09 ; 9 714: 90 e0 ldi r25, 0x00 ; 0 716: 90 93 f9 01 sts 0x01F9, r25 71a: 80 93 f8 01 sts 0x01F8, r24 71e: 65 c3 rjmp .+1738 ; 0xdea } else if (isdigit(inchar)) 720: 8c 2f mov r24, r28 722: 99 27 eor r25, r25 724: 0e 94 b3 07 call 0xf66 728: 89 2b or r24, r25 72a: a1 f0 breq .+40 ; 0x754 { addr *= 10; 72c: 90 91 fa 01 lds r25, 0x01FA addr += (inchar - '0'); 730: 8a e0 ldi r24, 0x0A ; 10 732: 98 9f mul r25, r24 734: 80 2d mov r24, r0 736: 11 24 eor r1, r1 738: 8c 0f add r24, r28 73a: 80 53 subi r24, 0x30 ; 48 73c: 80 93 fa 01 sts 0x01FA, r24 if (addr > MAX_AID_BUS_ADDRESS) 740: 80 31 cpi r24, 0x10 ; 16 742: 08 f4 brcc .+2 ; 0x746 744: 52 c3 rjmp .+1700 ; 0xdea { cmd_state = ERROR; 746: 81 e0 ldi r24, 0x01 ; 1 748: 90 e0 ldi r25, 0x00 ; 0 74a: 90 93 f9 01 sts 0x01F9, r25 74e: 80 93 f8 01 sts 0x01F8, r24 752: 4b c3 rjmp .+1686 ; 0xdea } } else if (isEOLchar(inchar)) 754: ca 30 cpi r28, 0x0A ; 10 756: 11 f0 breq .+4 ; 0x75c 758: cd 30 cpi r28, 0x0D ; 13 75a: 19 f4 brne .+6 ; 0x762 { err_then_INIT(); 75c: 0e 94 1a 02 call 0x434 760: 44 c3 rjmp .+1672 ; 0xdea } else { cmd_state = ERROR; 762: 81 e0 ldi r24, 0x01 ; 1 764: 90 e0 ldi r25, 0x00 ; 0 766: 90 93 f9 01 sts 0x01F9, r25 76a: 80 93 f8 01 sts 0x01F8, r24 } break; 76e: 3d c3 rjmp .+1658 ; 0xdea case W_A_: if (isdigit(inchar)) 770: 0c 2f mov r16, r28 772: 11 27 eor r17, r17 774: c8 01 movw r24, r16 776: 0e 94 b3 07 call 0xf66 77a: 89 2b or r24, r25 77c: 69 f0 breq .+26 ; 0x798 { data = inchar - '0'; 77e: 00 53 subi r16, 0x30 ; 48 780: 10 40 sbci r17, 0x00 ; 0 782: 10 93 fc 01 sts 0x01FC, r17 786: 00 93 fb 01 sts 0x01FB, r16 cmd_state = W_A_D; 78a: 8a e0 ldi r24, 0x0A ; 10 78c: 90 e0 ldi r25, 0x00 ; 0 78e: 90 93 f9 01 sts 0x01F9, r25 792: 80 93 f8 01 sts 0x01F8, r24 796: 29 c3 rjmp .+1618 ; 0xdea } else if (isWSchar(inchar)) 798: c0 32 cpi r28, 0x20 ; 32 79a: 09 f4 brne .+2 ; 0x79e 79c: 26 c3 rjmp .+1612 ; 0xdea 79e: c9 30 cpi r28, 0x09 ; 9 7a0: 09 f4 brne .+2 ; 0x7a4 7a2: 23 c3 rjmp .+1606 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) 7a4: ca 30 cpi r28, 0x0A ; 10 7a6: 11 f0 breq .+4 ; 0x7ac 7a8: cd 30 cpi r28, 0x0D ; 13 7aa: 19 f4 brne .+6 ; 0x7b2 { err_then_INIT(); 7ac: 0e 94 1a 02 call 0x434 7b0: 1c c3 rjmp .+1592 ; 0xdea } else { cmd_state = ERROR; 7b2: 81 e0 ldi r24, 0x01 ; 1 7b4: 90 e0 ldi r25, 0x00 ; 0 7b6: 90 93 f9 01 sts 0x01F9, r25 7ba: 80 93 f8 01 sts 0x01F8, r24 } break; 7be: 15 c3 rjmp .+1578 ; 0xdea case W_A_D: if (isdigit(inchar)) 7c0: 0c 2f mov r16, r28 7c2: 11 27 eor r17, r17 7c4: c8 01 movw r24, r16 7c6: 0e 94 b3 07 call 0xf66 7ca: 89 2b or r24, r25 7cc: 09 f1 breq .+66 ; 0x810 { data *= 10; 7ce: 20 91 fb 01 lds r18, 0x01FB 7d2: 30 91 fc 01 lds r19, 0x01FC 7d6: c9 01 movw r24, r18 7d8: f3 e0 ldi r31, 0x03 ; 3 7da: 88 0f add r24, r24 7dc: 99 1f adc r25, r25 7de: fa 95 dec r31 7e0: e1 f7 brne .-8 ; 0x7da 7e2: 82 0f add r24, r18 7e4: 93 1f adc r25, r19 7e6: 82 0f add r24, r18 7e8: 93 1f adc r25, r19 data += inchar - '0'; 7ea: 80 0f add r24, r16 7ec: 91 1f adc r25, r17 7ee: c0 97 sbiw r24, 0x30 ; 48 7f0: 90 93 fc 01 sts 0x01FC, r25 7f4: 80 93 fb 01 sts 0x01FB, r24 if (data > MAX_AID_BUS_DATA) 7f8: 8f 3f cpi r24, 0xFF ; 255 7fa: 91 05 cpc r25, r1 7fc: 09 f0 breq .+2 ; 0x800 7fe: 0c f4 brge .+2 ; 0x802 800: f4 c2 rjmp .+1512 ; 0xdea { cmd_state = ERROR; 802: 81 e0 ldi r24, 0x01 ; 1 804: 90 e0 ldi r25, 0x00 ; 0 806: 90 93 f9 01 sts 0x01F9, r25 80a: 80 93 f8 01 sts 0x01F8, r24 80e: ed c2 rjmp .+1498 ; 0xdea } } else if (isEOLchar(inchar)) 810: ca 30 cpi r28, 0x0A ; 10 812: 11 f0 breq .+4 ; 0x818 814: cd 30 cpi r28, 0x0D ; 13 816: 49 f4 brne .+18 ; 0x82a { aid_bus_write(addr,data); 818: 60 91 fb 01 lds r22, 0x01FB 81c: 80 91 fa 01 lds r24, 0x01FA 820: 0e 94 bb 00 call 0x176 ack_then_INIT(); 824: 0e 94 09 02 call 0x412 828: e0 c2 rjmp .+1472 ; 0xdea } else { cmd_state = ERROR; 82a: 81 e0 ldi r24, 0x01 ; 1 82c: 90 e0 ldi r25, 0x00 ; 0 82e: 90 93 f9 01 sts 0x01F9, r25 832: 80 93 f8 01 sts 0x01F8, r24 } break; 836: d9 c2 rjmp .+1458 ; 0xdea case P: if (isWSchar(inchar)) 838: c0 32 cpi r28, 0x20 ; 32 83a: 11 f0 breq .+4 ; 0x840 83c: c9 30 cpi r28, 0x09 ; 9 83e: 39 f4 brne .+14 ; 0x84e { cmd_state = P_; 840: 8c e0 ldi r24, 0x0C ; 12 842: 90 e0 ldi r25, 0x00 ; 0 844: 90 93 f9 01 sts 0x01F9, r25 848: 80 93 f8 01 sts 0x01F8, r24 84c: ce c2 rjmp .+1436 ; 0xdea } else if (inchar=='f') 84e: c6 36 cpi r28, 0x66 ; 102 850: 39 f4 brne .+14 ; 0x860 { cmd_state = PF; 852: 80 e1 ldi r24, 0x10 ; 16 854: 90 e0 ldi r25, 0x00 ; 0 856: 90 93 f9 01 sts 0x01F9, r25 85a: 80 93 f8 01 sts 0x01F8, r24 85e: c5 c2 rjmp .+1418 ; 0xdea } else if (isEOLchar(inchar)) 860: ca 30 cpi r28, 0x0A ; 10 862: 11 f0 breq .+4 ; 0x868 864: cd 30 cpi r28, 0x0D ; 13 866: 19 f4 brne .+6 ; 0x86e { err_then_INIT(); 868: 0e 94 1a 02 call 0x434 86c: be c2 rjmp .+1404 ; 0xdea } else { cmd_state = ERROR; 86e: 81 e0 ldi r24, 0x01 ; 1 870: 90 e0 ldi r25, 0x00 ; 0 872: 90 93 f9 01 sts 0x01F9, r25 876: 80 93 f8 01 sts 0x01F8, r24 } break; 87a: b7 c2 rjmp .+1390 ; 0xdea case P_: /* AVR models have four PWM chanels */ /* 040901 MPW */ if (inchar >='0' && inchar <= '3') /* 040901 MPW */ 87c: 8c 2f mov r24, r28 87e: 80 53 subi r24, 0x30 ; 48 880: 84 30 cpi r24, 0x04 ; 4 882: 48 f4 brcc .+18 ; 0x896 { addr = inchar - '0'; 884: 80 93 fa 01 sts 0x01FA, r24 cmd_state = P_A; 888: 8d e0 ldi r24, 0x0D ; 13 88a: 90 e0 ldi r25, 0x00 ; 0 88c: 90 93 f9 01 sts 0x01F9, r25 890: 80 93 f8 01 sts 0x01F8, r24 894: aa c2 rjmp .+1364 ; 0xdea } else if (isWSchar(inchar)) 896: c0 32 cpi r28, 0x20 ; 32 898: 09 f4 brne .+2 ; 0x89c 89a: a7 c2 rjmp .+1358 ; 0xdea 89c: c9 30 cpi r28, 0x09 ; 9 89e: 09 f4 brne .+2 ; 0x8a2 8a0: a4 c2 rjmp .+1352 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) 8a2: ca 30 cpi r28, 0x0A ; 10 8a4: 11 f0 breq .+4 ; 0x8aa 8a6: cd 30 cpi r28, 0x0D ; 13 8a8: 19 f4 brne .+6 ; 0x8b0 { err_then_INIT(); 8aa: 0e 94 1a 02 call 0x434 8ae: 9d c2 rjmp .+1338 ; 0xdea } else { cmd_state = ERROR; 8b0: 81 e0 ldi r24, 0x01 ; 1 8b2: 90 e0 ldi r25, 0x00 ; 0 8b4: 90 93 f9 01 sts 0x01F9, r25 8b8: 80 93 f8 01 sts 0x01F8, r24 } break; 8bc: 96 c2 rjmp .+1324 ; 0xdea case P_A: if (isWSchar(inchar)) 8be: c0 32 cpi r28, 0x20 ; 32 8c0: 11 f0 breq .+4 ; 0x8c6 8c2: c9 30 cpi r28, 0x09 ; 9 8c4: 39 f4 brne .+14 ; 0x8d4 { cmd_state = P_A_; 8c6: 8e e0 ldi r24, 0x0E ; 14 8c8: 90 e0 ldi r25, 0x00 ; 0 8ca: 90 93 f9 01 sts 0x01F9, r25 8ce: 80 93 f8 01 sts 0x01F8, r24 8d2: 8b c2 rjmp .+1302 ; 0xdea } else if (isEOLchar(inchar)) 8d4: ca 30 cpi r28, 0x0A ; 10 8d6: 11 f0 breq .+4 ; 0x8dc 8d8: cd 30 cpi r28, 0x0D ; 13 8da: 19 f4 brne .+6 ; 0x8e2 { err_then_INIT(); 8dc: 0e 94 1a 02 call 0x434 8e0: 84 c2 rjmp .+1288 ; 0xdea } else { cmd_state = ERROR; 8e2: 81 e0 ldi r24, 0x01 ; 1 8e4: 90 e0 ldi r25, 0x00 ; 0 8e6: 90 93 f9 01 sts 0x01F9, r25 8ea: 80 93 f8 01 sts 0x01F8, r24 } break; 8ee: 7d c2 rjmp .+1274 ; 0xdea case P_A_: if (isdigit(inchar)) 8f0: 0c 2f mov r16, r28 8f2: 11 27 eor r17, r17 8f4: c8 01 movw r24, r16 8f6: 0e 94 b3 07 call 0xf66 8fa: 89 2b or r24, r25 8fc: 69 f0 breq .+26 ; 0x918 { data = inchar - '0'; 8fe: 00 53 subi r16, 0x30 ; 48 900: 10 40 sbci r17, 0x00 ; 0 902: 10 93 fc 01 sts 0x01FC, r17 906: 00 93 fb 01 sts 0x01FB, r16 cmd_state = P_A_DC; 90a: 8f e0 ldi r24, 0x0F ; 15 90c: 90 e0 ldi r25, 0x00 ; 0 90e: 90 93 f9 01 sts 0x01F9, r25 912: 80 93 f8 01 sts 0x01F8, r24 916: 69 c2 rjmp .+1234 ; 0xdea } else if (isWSchar(inchar)) 918: c0 32 cpi r28, 0x20 ; 32 91a: 09 f4 brne .+2 ; 0x91e 91c: 66 c2 rjmp .+1228 ; 0xdea 91e: c9 30 cpi r28, 0x09 ; 9 920: 09 f4 brne .+2 ; 0x924 922: 63 c2 rjmp .+1222 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) 924: ca 30 cpi r28, 0x0A ; 10 926: 11 f0 breq .+4 ; 0x92c 928: cd 30 cpi r28, 0x0D ; 13 92a: 19 f4 brne .+6 ; 0x932 { err_then_INIT(); 92c: 0e 94 1a 02 call 0x434 930: 5c c2 rjmp .+1208 ; 0xdea } else { cmd_state = ERROR; 932: 81 e0 ldi r24, 0x01 ; 1 934: 90 e0 ldi r25, 0x00 ; 0 936: 90 93 f9 01 sts 0x01F9, r25 93a: 80 93 f8 01 sts 0x01F8, r24 } break; 93e: 55 c2 rjmp .+1194 ; 0xdea case P_A_DC: if (isdigit(inchar)) 940: 0c 2f mov r16, r28 942: 11 27 eor r17, r17 944: c8 01 movw r24, r16 946: 0e 94 b3 07 call 0xf66 94a: 89 2b or r24, r25 94c: 01 f1 breq .+64 ; 0x98e { data *= 10; 94e: 20 91 fb 01 lds r18, 0x01FB 952: 30 91 fc 01 lds r19, 0x01FC 956: c9 01 movw r24, r18 958: e3 e0 ldi r30, 0x03 ; 3 95a: 88 0f add r24, r24 95c: 99 1f adc r25, r25 95e: ea 95 dec r30 960: e1 f7 brne .-8 ; 0x95a 962: 82 0f add r24, r18 964: 93 1f adc r25, r19 966: 82 0f add r24, r18 968: 93 1f adc r25, r19 data += inchar - '0'; 96a: 80 0f add r24, r16 96c: 91 1f adc r25, r17 96e: c0 97 sbiw r24, 0x30 ; 48 970: 90 93 fc 01 sts 0x01FC, r25 974: 80 93 fb 01 sts 0x01FB, r24 if (data > 100) 978: 85 36 cpi r24, 0x65 ; 101 97a: 91 05 cpc r25, r1 97c: 0c f4 brge .+2 ; 0x980 97e: 35 c2 rjmp .+1130 ; 0xdea { /* By definition, the duty cycle is not greater than 100% */ cmd_state = ERROR; 980: 81 e0 ldi r24, 0x01 ; 1 982: 90 e0 ldi r25, 0x00 ; 0 984: 90 93 f9 01 sts 0x01F9, r25 988: 80 93 f8 01 sts 0x01F8, r24 98c: 2e c2 rjmp .+1116 ; 0xdea } } else if (isEOLchar(inchar)) 98e: ca 30 cpi r28, 0x0A ; 10 990: 11 f0 breq .+4 ; 0x996 992: cd 30 cpi r28, 0x0D ; 13 994: 59 f4 brne .+22 ; 0x9ac { set_pwm_duty_cycle(addr, data); 996: 60 91 fb 01 lds r22, 0x01FB 99a: 70 91 fc 01 lds r23, 0x01FC 99e: 80 91 fa 01 lds r24, 0x01FA 9a2: 0e 94 e8 00 call 0x1d0 ack_then_INIT(); 9a6: 0e 94 09 02 call 0x412 9aa: 1f c2 rjmp .+1086 ; 0xdea } else { cmd_state = ERROR; 9ac: 81 e0 ldi r24, 0x01 ; 1 9ae: 90 e0 ldi r25, 0x00 ; 0 9b0: 90 93 f9 01 sts 0x01F9, r25 9b4: 80 93 f8 01 sts 0x01F8, r24 } break; 9b8: 18 c2 rjmp .+1072 ; 0xdea case PF: if (isWSchar(inchar)) 9ba: c0 32 cpi r28, 0x20 ; 32 9bc: 11 f0 breq .+4 ; 0x9c2 9be: c9 30 cpi r28, 0x09 ; 9 9c0: 39 f4 brne .+14 ; 0x9d0 { cmd_state = PF_; 9c2: 81 e1 ldi r24, 0x11 ; 17 9c4: 90 e0 ldi r25, 0x00 ; 0 9c6: 90 93 f9 01 sts 0x01F9, r25 9ca: 80 93 f8 01 sts 0x01F8, r24 9ce: 0d c2 rjmp .+1050 ; 0xdea } else if (isEOLchar(inchar)) 9d0: ca 30 cpi r28, 0x0A ; 10 9d2: 11 f0 breq .+4 ; 0x9d8 9d4: cd 30 cpi r28, 0x0D ; 13 9d6: 19 f4 brne .+6 ; 0x9de { err_then_INIT(); 9d8: 0e 94 1a 02 call 0x434 9dc: 06 c2 rjmp .+1036 ; 0xdea } else { cmd_state = ERROR; 9de: 81 e0 ldi r24, 0x01 ; 1 9e0: 90 e0 ldi r25, 0x00 ; 0 9e2: 90 93 f9 01 sts 0x01F9, r25 9e6: 80 93 f8 01 sts 0x01F8, r24 } break; 9ea: ff c1 rjmp .+1022 ; 0xdea case PF_: if (isdigit(inchar)) 9ec: 0c 2f mov r16, r28 9ee: 11 27 eor r17, r17 9f0: c8 01 movw r24, r16 9f2: 0e 94 b3 07 call 0xf66 9f6: 89 2b or r24, r25 9f8: 69 f0 breq .+26 ; 0xa14 { data = inchar - '0'; 9fa: 00 53 subi r16, 0x30 ; 48 9fc: 10 40 sbci r17, 0x00 ; 0 9fe: 10 93 fc 01 sts 0x01FC, r17 a02: 00 93 fb 01 sts 0x01FB, r16 cmd_state = PF_F; a06: 82 e1 ldi r24, 0x12 ; 18 a08: 90 e0 ldi r25, 0x00 ; 0 a0a: 90 93 f9 01 sts 0x01F9, r25 a0e: 80 93 f8 01 sts 0x01F8, r24 a12: eb c1 rjmp .+982 ; 0xdea } else if (inchar=='!') a14: c1 32 cpi r28, 0x21 ; 33 a16: 39 f4 brne .+14 ; 0xa26 { cmd_state = PF_default; a18: 83 e1 ldi r24, 0x13 ; 19 a1a: 90 e0 ldi r25, 0x00 ; 0 a1c: 90 93 f9 01 sts 0x01F9, r25 a20: 80 93 f8 01 sts 0x01F8, r24 a24: e2 c1 rjmp .+964 ; 0xdea } else if (isWSchar(inchar)) a26: c0 32 cpi r28, 0x20 ; 32 a28: 09 f4 brne .+2 ; 0xa2c a2a: df c1 rjmp .+958 ; 0xdea a2c: c9 30 cpi r28, 0x09 ; 9 a2e: 09 f4 brne .+2 ; 0xa32 a30: dc c1 rjmp .+952 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) a32: ca 30 cpi r28, 0x0A ; 10 a34: 11 f0 breq .+4 ; 0xa3a a36: cd 30 cpi r28, 0x0D ; 13 a38: 19 f4 brne .+6 ; 0xa40 { err_then_INIT(); a3a: 0e 94 1a 02 call 0x434 a3e: d5 c1 rjmp .+938 ; 0xdea } else { cmd_state = ERROR; a40: 81 e0 ldi r24, 0x01 ; 1 a42: 90 e0 ldi r25, 0x00 ; 0 a44: 90 93 f9 01 sts 0x01F9, r25 a48: 80 93 f8 01 sts 0x01F8, r24 } break; a4c: ce c1 rjmp .+924 ; 0xdea case PF_F: if (isdigit(inchar)) a4e: 0c 2f mov r16, r28 a50: 11 27 eor r17, r17 a52: c8 01 movw r24, r16 a54: 0e 94 b3 07 call 0xf66 a58: 89 2b or r24, r25 a5a: 01 f1 breq .+64 ; 0xa9c { data *= 10; a5c: 20 91 fb 01 lds r18, 0x01FB a60: 30 91 fc 01 lds r19, 0x01FC a64: c9 01 movw r24, r18 a66: 73 e0 ldi r23, 0x03 ; 3 a68: 88 0f add r24, r24 a6a: 99 1f adc r25, r25 a6c: 7a 95 dec r23 a6e: e1 f7 brne .-8 ; 0xa68 a70: 82 0f add r24, r18 a72: 93 1f adc r25, r19 a74: 82 0f add r24, r18 a76: 93 1f adc r25, r19 data += inchar - '0'; a78: 80 0f add r24, r16 a7a: 91 1f adc r25, r17 a7c: c0 97 sbiw r24, 0x30 ; 48 a7e: 90 93 fc 01 sts 0x01FC, r25 a82: 80 93 fb 01 sts 0x01FB, r24 if (data > MAX_PWM_FREQ) a86: 85 5c subi r24, 0xC5 ; 197 a88: 99 40 sbci r25, 0x09 ; 9 a8a: 0c f4 brge .+2 ; 0xa8e a8c: ae c1 rjmp .+860 ; 0xdea { cmd_state = ERROR; a8e: 81 e0 ldi r24, 0x01 ; 1 a90: 90 e0 ldi r25, 0x00 ; 0 a92: 90 93 f9 01 sts 0x01F9, r25 a96: 80 93 f8 01 sts 0x01F8, r24 a9a: a7 c1 rjmp .+846 ; 0xdea } } else if (isEOLchar(inchar)) a9c: ca 30 cpi r28, 0x0A ; 10 a9e: 11 f0 breq .+4 ; 0xaa4 aa0: cd 30 cpi r28, 0x0D ; 13 aa2: 49 f4 brne .+18 ; 0xab6 { set_pwm_frequency(data); aa4: 80 91 fb 01 lds r24, 0x01FB aa8: 90 91 fc 01 lds r25, 0x01FC aac: 0e 94 34 01 call 0x268 ack_then_INIT(); ab0: 0e 94 09 02 call 0x412 ab4: 9a c1 rjmp .+820 ; 0xdea } else { cmd_state = ERROR; ab6: 81 e0 ldi r24, 0x01 ; 1 ab8: 90 e0 ldi r25, 0x00 ; 0 aba: 90 93 f9 01 sts 0x01F9, r25 abe: 80 93 f8 01 sts 0x01F8, r24 } break; ac2: 93 c1 rjmp .+806 ; 0xdea case PF_default: if (isEOLchar(inchar)) ac4: ca 30 cpi r28, 0x0A ; 10 ac6: 11 f0 breq .+4 ; 0xacc ac8: cd 30 cpi r28, 0x0D ; 13 aca: 39 f4 brne .+14 ; 0xada { set_pwm_frequency(DEFAULT_PWM_FREQ); acc: 84 e1 ldi r24, 0x14 ; 20 ace: 90 e0 ldi r25, 0x00 ; 0 ad0: 0e 94 34 01 call 0x268 ack_then_INIT(); ad4: 0e 94 09 02 call 0x412 ad8: 88 c1 rjmp .+784 ; 0xdea } else { cmd_state = ERROR; ada: 81 e0 ldi r24, 0x01 ; 1 adc: 90 e0 ldi r25, 0x00 ; 0 ade: 90 93 f9 01 sts 0x01F9, r25 ae2: 80 93 f8 01 sts 0x01F8, r24 } break; ae6: 81 c1 rjmp .+770 ; 0xdea case A: if (isWSchar(inchar)) ae8: c0 32 cpi r28, 0x20 ; 32 aea: 11 f0 breq .+4 ; 0xaf0 aec: c9 30 cpi r28, 0x09 ; 9 aee: 39 f4 brne .+14 ; 0xafe { cmd_state = A_; af0: 85 e1 ldi r24, 0x15 ; 21 af2: 90 e0 ldi r25, 0x00 ; 0 af4: 90 93 f9 01 sts 0x01F9, r25 af8: 80 93 f8 01 sts 0x01F8, r24 afc: 76 c1 rjmp .+748 ; 0xdea } else if (isEOLchar(inchar)) afe: ca 30 cpi r28, 0x0A ; 10 b00: 11 f0 breq .+4 ; 0xb06 b02: cd 30 cpi r28, 0x0D ; 13 b04: 19 f4 brne .+6 ; 0xb0c { err_then_INIT(); b06: 0e 94 1a 02 call 0x434 b0a: 6f c1 rjmp .+734 ; 0xdea } else { cmd_state = ERROR; b0c: 81 e0 ldi r24, 0x01 ; 1 b0e: 90 e0 ldi r25, 0x00 ; 0 b10: 90 93 f9 01 sts 0x01F9, r25 b14: 80 93 f8 01 sts 0x01F8, r24 } break; b18: 68 c1 rjmp .+720 ; 0xdea case A_: if (inchar>='0' && inchar<='7') b1a: 8c 2f mov r24, r28 b1c: 80 53 subi r24, 0x30 ; 48 b1e: 88 30 cpi r24, 0x08 ; 8 b20: 48 f4 brcc .+18 ; 0xb34 { addr = inchar - '0'; b22: 80 93 fa 01 sts 0x01FA, r24 cmd_state = A_A; b26: 86 e1 ldi r24, 0x16 ; 22 b28: 90 e0 ldi r25, 0x00 ; 0 b2a: 90 93 f9 01 sts 0x01F9, r25 b2e: 80 93 f8 01 sts 0x01F8, r24 b32: 5b c1 rjmp .+694 ; 0xdea } else if (inchar=='*') b34: ca 32 cpi r28, 0x2A ; 42 b36: 39 f4 brne .+14 ; 0xb46 { cmd_state = A_all; b38: 87 e1 ldi r24, 0x17 ; 23 b3a: 90 e0 ldi r25, 0x00 ; 0 b3c: 90 93 f9 01 sts 0x01F9, r25 b40: 80 93 f8 01 sts 0x01F8, r24 b44: 52 c1 rjmp .+676 ; 0xdea } else if (isWSchar(inchar)) b46: c0 32 cpi r28, 0x20 ; 32 b48: 09 f4 brne .+2 ; 0xb4c b4a: 4f c1 rjmp .+670 ; 0xdea b4c: c9 30 cpi r28, 0x09 ; 9 b4e: 09 f4 brne .+2 ; 0xb52 b50: 4c c1 rjmp .+664 ; 0xdea { /* Any amount of whitespace is ok. */ } else if (isEOLchar(inchar)) b52: ca 30 cpi r28, 0x0A ; 10 b54: 11 f0 breq .+4 ; 0xb5a b56: cd 30 cpi r28, 0x0D ; 13 b58: 19 f4 brne .+6 ; 0xb60 { err_then_INIT(); b5a: 0e 94 1a 02 call 0x434 b5e: 45 c1 rjmp .+650 ; 0xdea } else { cmd_state = ERROR; b60: 81 e0 ldi r24, 0x01 ; 1 b62: 90 e0 ldi r25, 0x00 ; 0 b64: 90 93 f9 01 sts 0x01F9, r25 b68: 80 93 f8 01 sts 0x01F8, r24 } break; b6c: 3e c1 rjmp .+636 ; 0xdea case A_A: if (isEOLchar(inchar)) b6e: ca 30 cpi r28, 0x0A ; 10 b70: 11 f0 breq .+4 ; 0xb76 b72: cd 30 cpi r28, 0x0D ; 13 b74: a9 f4 brne .+42 ; 0xba0 { data = get_ad(addr); b76: 80 91 fa 01 lds r24, 0x01FA b7a: 0e 94 4f 01 call 0x29e b7e: 90 93 fc 01 sts 0x01FC, r25 b82: 80 93 fb 01 sts 0x01FB, r24 puts(eol); b86: 8b ea ldi r24, 0xAB ; 171 b88: 91 e0 ldi r25, 0x01 ; 1 b8a: 0e 94 81 01 call 0x302 put_some_digits(data); b8e: 80 91 fb 01 lds r24, 0x01FB b92: 90 91 fc 01 lds r25, 0x01FC b96: 0e 94 c3 01 call 0x386 ack_then_INIT(); b9a: 0e 94 09 02 call 0x412 b9e: 25 c1 rjmp .+586 ; 0xdea } else { cmd_state = ERROR; ba0: 81 e0 ldi r24, 0x01 ; 1 ba2: 90 e0 ldi r25, 0x00 ; 0 ba4: 90 93 f9 01 sts 0x01F9, r25 ba8: 80 93 f8 01 sts 0x01F8, r24 } break; bac: 1e c1 rjmp .+572 ; 0xdea case A_all: if (isEOLchar(inchar)) bae: ca 30 cpi r28, 0x0A ; 10 bb0: 11 f0 breq .+4 ; 0xbb6 bb2: cd 30 cpi r28, 0x0D ; 13 bb4: e9 f4 brne .+58 ; 0xbf0 { puts(eol); bb6: 8b ea ldi r24, 0xAB ; 171 bb8: 91 e0 ldi r25, 0x01 ; 1 bba: 0e 94 81 01 call 0x302 for (addr=0; addr<=7; addr++) bbe: 10 92 fa 01 sts 0x01FA, r1 { data = get_ad(addr); bc2: 80 91 fa 01 lds r24, 0x01FA bc6: 0e 94 4f 01 call 0x29e bca: 90 93 fc 01 sts 0x01FC, r25 bce: 80 93 fb 01 sts 0x01FB, r24 put_some_digits(data); bd2: 0e 94 c3 01 call 0x386 putch(' '); bd6: 80 e2 ldi r24, 0x20 ; 32 bd8: 0e 94 88 00 call 0x110 bdc: 80 91 fa 01 lds r24, 0x01FA be0: 8f 5f subi r24, 0xFF ; 255 be2: 80 93 fa 01 sts 0x01FA, r24 be6: 88 30 cpi r24, 0x08 ; 8 be8: 60 f3 brcs .-40 ; 0xbc2 } ack_then_INIT(); bea: 0e 94 09 02 call 0x412 bee: fd c0 rjmp .+506 ; 0xdea } else { cmd_state = ERROR; bf0: 81 e0 ldi r24, 0x01 ; 1 bf2: 90 e0 ldi r25, 0x00 ; 0 bf4: 90 93 f9 01 sts 0x01F9, r25 bf8: 80 93 f8 01 sts 0x01F8, r24 } break; bfc: f6 c0 rjmp .+492 ; 0xdea case E: if (inchar=='o') bfe: cf 36 cpi r28, 0x6F ; 111 c00: 39 f4 brne .+14 ; 0xc10 { cmd_state = EO; c02: 89 e1 ldi r24, 0x19 ; 25 c04: 90 e0 ldi r25, 0x00 ; 0 c06: 90 93 f9 01 sts 0x01F9, r25 c0a: 80 93 f8 01 sts 0x01F8, r24 c0e: ed c0 rjmp .+474 ; 0xdea } else if (isEOLchar(inchar)) c10: ca 30 cpi r28, 0x0A ; 10 c12: 11 f0 breq .+4 ; 0xc18 c14: cd 30 cpi r28, 0x0D ; 13 c16: 19 f4 brne .+6 ; 0xc1e { err_then_INIT(); c18: 0e 94 1a 02 call 0x434 c1c: e6 c0 rjmp .+460 ; 0xdea } else { cmd_state = ERROR; c1e: 81 e0 ldi r24, 0x01 ; 1 c20: 90 e0 ldi r25, 0x00 ; 0 c22: 90 93 f9 01 sts 0x01F9, r25 c26: 80 93 f8 01 sts 0x01F8, r24 } break; c2a: df c0 rjmp .+446 ; 0xdea case EO: if (inchar=='l') c2c: cc 36 cpi r28, 0x6C ; 108 c2e: 39 f4 brne .+14 ; 0xc3e { cmd_state = EOL; c30: 8a e1 ldi r24, 0x1A ; 26 c32: 90 e0 ldi r25, 0x00 ; 0 c34: 90 93 f9 01 sts 0x01F9, r25 c38: 80 93 f8 01 sts 0x01F8, r24 c3c: d6 c0 rjmp .+428 ; 0xdea } else if (isEOLchar(inchar)) c3e: ca 30 cpi r28, 0x0A ; 10 c40: 11 f0 breq .+4 ; 0xc46 c42: cd 30 cpi r28, 0x0D ; 13 c44: 19 f4 brne .+6 ; 0xc4c { err_then_INIT(); c46: 0e 94 1a 02 call 0x434 c4a: cf c0 rjmp .+414 ; 0xdea } else { cmd_state = ERROR; c4c: 81 e0 ldi r24, 0x01 ; 1 c4e: 90 e0 ldi r25, 0x00 ; 0 c50: 90 93 f9 01 sts 0x01F9, r25 c54: 80 93 f8 01 sts 0x01F8, r24 } break; c58: c8 c0 rjmp .+400 ; 0xdea case EOL: if (isWSchar(inchar)) c5a: c0 32 cpi r28, 0x20 ; 32 c5c: 11 f0 breq .+4 ; 0xc62 c5e: c9 30 cpi r28, 0x09 ; 9 c60: 39 f4 brne .+14 ; 0xc70 { cmd_state = EOL_; c62: 8b e1 ldi r24, 0x1B ; 27 c64: 90 e0 ldi r25, 0x00 ; 0 c66: 90 93 f9 01 sts 0x01F9, r25 c6a: 80 93 f8 01 sts 0x01F8, r24 c6e: bd c0 rjmp .+378 ; 0xdea } else if (isEOLchar(inchar)) c70: ca 30 cpi r28, 0x0A ; 10 c72: 11 f0 breq .+4 ; 0xc78 c74: cd 30 cpi r28, 0x0D ; 13 c76: 19 f4 brne .+6 ; 0xc7e { err_then_INIT(); c78: 0e 94 1a 02 call 0x434 c7c: b6 c0 rjmp .+364 ; 0xdea } else { cmd_state = ERROR; c7e: 81 e0 ldi r24, 0x01 ; 1 c80: 90 e0 ldi r25, 0x00 ; 0 c82: 90 93 f9 01 sts 0x01F9, r25 c86: 80 93 f8 01 sts 0x01F8, r24 } break; c8a: af c0 rjmp .+350 ; 0xdea case EOL_: if (inchar=='r') c8c: c2 37 cpi r28, 0x72 ; 114 c8e: 39 f4 brne .+14 ; 0xc9e { cmd_state = EOL_R; c90: 8c e1 ldi r24, 0x1C ; 28 c92: 90 e0 ldi r25, 0x00 ; 0 c94: 90 93 f9 01 sts 0x01F9, r25 c98: 80 93 f8 01 sts 0x01F8, r24 c9c: a6 c0 rjmp .+332 ; 0xdea } else if (inchar=='n') c9e: ce 36 cpi r28, 0x6E ; 110 ca0: 39 f4 brne .+14 ; 0xcb0 { cmd_state = EOL_N; ca2: 8d e1 ldi r24, 0x1D ; 29 ca4: 90 e0 ldi r25, 0x00 ; 0 ca6: 90 93 f9 01 sts 0x01F9, r25 caa: 80 93 f8 01 sts 0x01F8, r24 cae: 9d c0 rjmp .+314 ; 0xdea } else if (isEOLchar(inchar)) cb0: ca 30 cpi r28, 0x0A ; 10 cb2: 11 f0 breq .+4 ; 0xcb8 cb4: cd 30 cpi r28, 0x0D ; 13 cb6: 19 f4 brne .+6 ; 0xcbe { err_then_INIT(); cb8: 0e 94 1a 02 call 0x434 cbc: 96 c0 rjmp .+300 ; 0xdea } else { cmd_state = ERROR; cbe: 81 e0 ldi r24, 0x01 ; 1 cc0: 90 e0 ldi r25, 0x00 ; 0 cc2: 90 93 f9 01 sts 0x01F9, r25 cc6: 80 93 f8 01 sts 0x01F8, r24 } break; cca: 8f c0 rjmp .+286 ; 0xdea case EOL_R: if (inchar=='n') ccc: ce 36 cpi r28, 0x6E ; 110 cce: 39 f4 brne .+14 ; 0xcde { cmd_state = EOL_RN; cd0: 8e e1 ldi r24, 0x1E ; 30 cd2: 90 e0 ldi r25, 0x00 ; 0 cd4: 90 93 f9 01 sts 0x01F9, r25 cd8: 80 93 f8 01 sts 0x01F8, r24 cdc: 86 c0 rjmp .+268 ; 0xdea } else if (isEOLchar(inchar)) cde: ca 30 cpi r28, 0x0A ; 10 ce0: 11 f0 breq .+4 ; 0xce6 ce2: cd 30 cpi r28, 0x0D ; 13 ce4: 41 f4 brne .+16 ; 0xcf6 { eol[0] = '\r'; ce6: 8d e0 ldi r24, 0x0D ; 13 ce8: 80 93 ab 01 sts 0x01AB, r24 eol[1] = '\0'; cec: 10 92 ac 01 sts 0x01AC, r1 ack_then_INIT(); cf0: 0e 94 09 02 call 0x412 cf4: 7a c0 rjmp .+244 ; 0xdea } else { cmd_state = ERROR; cf6: 81 e0 ldi r24, 0x01 ; 1 cf8: 90 e0 ldi r25, 0x00 ; 0 cfa: 90 93 f9 01 sts 0x01F9, r25 cfe: 80 93 f8 01 sts 0x01F8, r24 } break; d02: 73 c0 rjmp .+230 ; 0xdea case EOL_N: if (isEOLchar(inchar)) d04: ca 30 cpi r28, 0x0A ; 10 d06: 11 f0 breq .+4 ; 0xd0c d08: cd 30 cpi r28, 0x0D ; 13 d0a: 41 f4 brne .+16 ; 0xd1c { eol[0] = '\n'; d0c: 8a e0 ldi r24, 0x0A ; 10 d0e: 80 93 ab 01 sts 0x01AB, r24 eol[1] = '\0'; d12: 10 92 ac 01 sts 0x01AC, r1 ack_then_INIT(); d16: 0e 94 09 02 call 0x412 d1a: 67 c0 rjmp .+206 ; 0xdea } else { cmd_state = ERROR; d1c: 81 e0 ldi r24, 0x01 ; 1 d1e: 90 e0 ldi r25, 0x00 ; 0 d20: 90 93 f9 01 sts 0x01F9, r25 d24: 80 93 f8 01 sts 0x01F8, r24 } break; d28: 60 c0 rjmp .+192 ; 0xdea case EOL_RN: if (isEOLchar(inchar)) d2a: ca 30 cpi r28, 0x0A ; 10 d2c: 11 f0 breq .+4 ; 0xd32 d2e: cd 30 cpi r28, 0x0D ; 13 d30: 59 f4 brne .+22 ; 0xd48 { eol[0] = '\r'; d32: 8d e0 ldi r24, 0x0D ; 13 d34: 80 93 ab 01 sts 0x01AB, r24 eol[1] = '\n'; d38: 8a e0 ldi r24, 0x0A ; 10 d3a: 80 93 ac 01 sts 0x01AC, r24 eol[2] = '\0'; d3e: 10 92 ad 01 sts 0x01AD, r1 ack_then_INIT(); d42: 0e 94 09 02 call 0x412 d46: 51 c0 rjmp .+162 ; 0xdea } else { cmd_state = ERROR; d48: 81 e0 ldi r24, 0x01 ; 1 d4a: 90 e0 ldi r25, 0x00 ; 0 d4c: 90 93 f9 01 sts 0x01F9, r25 d50: 80 93 f8 01 sts 0x01F8, r24 } break; d54: 4a c0 rjmp .+148 ; 0xdea case H: if (isEOLchar(inchar)) d56: ca 30 cpi r28, 0x0A ; 10 d58: 19 f0 breq .+6 ; 0xd60 d5a: cd 30 cpi r28, 0x0D ; 13 d5c: 09 f0 breq .+2 ; 0xd60 d5e: 3f c0 rjmp .+126 ; 0xdde { puts(eol); d60: 8b ea ldi r24, 0xAB ; 171 d62: 91 e0 ldi r25, 0x01 ; 1 d64: 0e 94 81 01 call 0x302 puts(help_text1); puts(eol); d68: 84 e8 ldi r24, 0x84 ; 132 d6a: 90 e0 ldi r25, 0x00 ; 0 d6c: 0e 94 81 01 call 0x302 d70: 8b ea ldi r24, 0xAB ; 171 d72: 91 e0 ldi r25, 0x01 ; 1 d74: 0e 94 81 01 call 0x302 puts(help_text2); puts(eol); d78: 8d ea ldi r24, 0xAD ; 173 d7a: 90 e0 ldi r25, 0x00 ; 0 d7c: 0e 94 81 01 call 0x302 d80: 8b ea ldi r24, 0xAB ; 171 d82: 91 e0 ldi r25, 0x01 ; 1 d84: 0e 94 81 01 call 0x302 puts(help_text3); puts(eol); d88: 88 ed ldi r24, 0xD8 ; 216 d8a: 90 e0 ldi r25, 0x00 ; 0 d8c: 0e 94 81 01 call 0x302 d90: 8b ea ldi r24, 0xAB ; 171 d92: 91 e0 ldi r25, 0x01 ; 1 d94: 0e 94 81 01 call 0x302 puts(help_text4); puts(eol); d98: 88 e0 ldi r24, 0x08 ; 8 d9a: 91 e0 ldi r25, 0x01 ; 1 d9c: 0e 94 81 01 call 0x302 da0: 8b ea ldi r24, 0xAB ; 171 da2: 91 e0 ldi r25, 0x01 ; 1 da4: 0e 94 81 01 call 0x302 puts(help_text5); puts(eol); da8: 87 e3 ldi r24, 0x37 ; 55 daa: 91 e0 ldi r25, 0x01 ; 1 dac: 0e 94 81 01 call 0x302 db0: 8b ea ldi r24, 0xAB ; 171 db2: 91 e0 ldi r25, 0x01 ; 1 db4: 0e 94 81 01 call 0x302 puts(help_text6); puts(eol); db8: 8b e5 ldi r24, 0x5B ; 91 dba: 91 e0 ldi r25, 0x01 ; 1 dbc: 0e 94 81 01 call 0x302 dc0: 8b ea ldi r24, 0xAB ; 171 dc2: 91 e0 ldi r25, 0x01 ; 1 dc4: 0e 94 81 01 call 0x302 puts(help_text7); puts(eol); dc8: 8a e8 ldi r24, 0x8A ; 138 dca: 91 e0 ldi r25, 0x01 ; 1 dcc: 0e 94 81 01 call 0x302 dd0: 8b ea ldi r24, 0xAB ; 171 dd2: 91 e0 ldi r25, 0x01 ; 1 dd4: 0e 94 81 01 call 0x302 ack_then_INIT(); dd8: 0e 94 09 02 call 0x412 ddc: 06 c0 rjmp .+12 ; 0xdea } else { cmd_state = ERROR; dde: 81 e0 ldi r24, 0x01 ; 1 de0: 90 e0 ldi r25, 0x00 ; 0 de2: 90 93 f9 01 sts 0x01F9, r25 de6: 80 93 f8 01 sts 0x01F8, r24 } break; /* case M: if (inchar=='s') { cmd_state = MS; } else if (inchar=='a') { cmd_state = MA; } else if (inchar=='r') { cmd_state = MR; } else { cmd_state = ERROR; } break; case MS: if (isEOLchar(inchar)) { for (addr=0; addr<16; addr++) { for (addr2=0; addr2<16; addr2++) { put_some_digits(map_table[addr][addr2]); putch(' '); } puts(eol); } puts(ack); puts(eol); } else { cmd_state = ERROR; } break; case MA: cmd_state = INIT; break; case MR: cmd_state = INIT; break; */ } /*switch*/ } /*next_char*/ dea: cf 91 pop r28 dec: 1f 91 pop r17 dee: 0f 91 pop r16 df0: 08 95 ret 00000df2
: const char main_c_rev[] = "$Revision: 1.4 $ main.c"; void main(void) { df2: cf e5 ldi r28, 0x5F ; 95 df4: d4 e0 ldi r29, 0x04 ; 4 df6: de bf out 0x3e, r29 ; 62 df8: cd bf out 0x3d, r28 ; 61 aid_mainboard_init(); dfa: 0e 94 79 01 call 0x2f2 /* Emit a greeting and some version information. */ puts( greeting); puts(eol); dfe: 8c ec ldi r24, 0xCC ; 204 e00: 91 e0 ldi r25, 0x01 ; 1 e02: 0e 94 81 01 call 0x302 e06: 8b ea ldi r24, 0xAB ; 171 e08: 91 e0 ldi r25, 0x01 ; 1 e0a: 0e 94 81 01 call 0x302 puts( main_c_rev); puts(eol); e0e: 80 ee ldi r24, 0xE0 ; 224 e10: 91 e0 ldi r25, 0x01 ; 1 e12: 0e 94 81 01 call 0x302 e16: 8b ea ldi r24, 0xAB ; 171 e18: 91 e0 ldi r25, 0x01 ; 1 e1a: 0e 94 81 01 call 0x302 puts(aid_cmd_c_rev); puts(eol); e1e: 8e ea ldi r24, 0xAE ; 174 e20: 91 e0 ldi r25, 0x01 ; 1 e22: 0e 94 81 01 call 0x302 e26: 8b ea ldi r24, 0xAB ; 171 e28: 91 e0 ldi r25, 0x01 ; 1 e2a: 0e 94 81 01 call 0x302 puts(aid_lib_c_rev); puts(eol); e2e: 80 e6 ldi r24, 0x60 ; 96 e30: 90 e0 ldi r25, 0x00 ; 0 e32: 0e 94 81 01 call 0x302 e36: 8b ea ldi r24, 0xAB ; 171 e38: 91 e0 ldi r25, 0x01 ; 1 e3a: 0e 94 81 01 call 0x302 /* Start the command processor. */ aid_cmd_restart(); e3e: 0e 94 fc 01 call 0x3f8 /* Main loop of the command processor state machine; runs forever. */ for(;;) { cmd_next_char(getch()); e42: 0e 94 83 00 call 0x106 e46: 0e 94 2b 02 call 0x456 e4a: fb cf rjmp .-10 ; 0xe42 00000e4c <__mulsi3>: } } e4c: 62 9f mul r22, r18 e4e: d0 01 movw r26, r0 e50: 73 9f mul r23, r19 e52: f0 01 movw r30, r0 e54: 82 9f mul r24, r18 e56: e0 0d add r30, r0 e58: f1 1d adc r31, r1 e5a: 64 9f mul r22, r20 e5c: e0 0d add r30, r0 e5e: f1 1d adc r31, r1 e60: 92 9f mul r25, r18 e62: f0 0d add r31, r0 e64: 83 9f mul r24, r19 e66: f0 0d add r31, r0 e68: 74 9f mul r23, r20 e6a: f0 0d add r31, r0 e6c: 65 9f mul r22, r21 e6e: f0 0d add r31, r0 e70: 99 27 eor r25, r25 e72: 72 9f mul r23, r18 e74: b0 0d add r27, r0 e76: e1 1d adc r30, r1 e78: f9 1f adc r31, r25 e7a: 63 9f mul r22, r19 e7c: b0 0d add r27, r0 e7e: e1 1d adc r30, r1 e80: f9 1f adc r31, r25 e82: bd 01 movw r22, r26 e84: cf 01 movw r24, r30 e86: 11 24 eor r1, r1 e88: 08 95 ret 00000e8a <__udivmodhi4>: e8a: aa 1b sub r26, r26 e8c: bb 1b sub r27, r27 e8e: 51 e1 ldi r21, 0x11 ; 17 e90: 07 c0 rjmp .+14 ; 0xea0 00000e92 <__udivmodhi4_loop>: e92: aa 1f adc r26, r26 e94: bb 1f adc r27, r27 e96: a6 17 cp r26, r22 e98: b7 07 cpc r27, r23 e9a: 10 f0 brcs .+4 ; 0xea0 e9c: a6 1b sub r26, r22 e9e: b7 0b sbc r27, r23 00000ea0 <__udivmodhi4_ep>: ea0: 88 1f adc r24, r24 ea2: 99 1f adc r25, r25 ea4: 5a 95 dec r21 ea6: a9 f7 brne .-22 ; 0xe92 ea8: 80 95 com r24 eaa: 90 95 com r25 eac: bc 01 movw r22, r24 eae: cd 01 movw r24, r26 eb0: 08 95 ret 00000eb2 <__divmodhi4>: eb2: 97 fb bst r25, 7 eb4: 09 2e mov r0, r25 eb6: 07 26 eor r0, r23 eb8: 0a d0 rcall .+20 ; 0xece eba: 77 fd sbrc r23, 7 ebc: 04 d0 rcall .+8 ; 0xec6 ebe: e5 df rcall .-54 ; 0xe8a ec0: 06 d0 rcall .+12 ; 0xece ec2: 00 20 and r0, r0 ec4: 1a f4 brpl .+6 ; 0xecc 00000ec6 <__divmodhi4_neg2>: ec6: 70 95 com r23 ec8: 61 95 neg r22 eca: 7f 4f sbci r23, 0xFF ; 255 00000ecc <__divmodhi4_exit>: ecc: 08 95 ret 00000ece <__divmodhi4_neg1>: ece: f6 f7 brtc .-4 ; 0xecc ed0: 90 95 com r25 ed2: 81 95 neg r24 ed4: 9f 4f sbci r25, 0xFF ; 255 ed6: 08 95 ret 00000ed8 <__divmodsi4>: ed8: 97 fb bst r25, 7 eda: 09 2e mov r0, r25 edc: 05 26 eor r0, r21 ede: 0e d0 rcall .+28 ; 0xefc ee0: 57 fd sbrc r21, 7 ee2: 04 d0 rcall .+8 ; 0xeec ee4: 14 d0 rcall .+40 ; 0xf0e ee6: 0a d0 rcall .+20 ; 0xefc ee8: 00 1c adc r0, r0 eea: 38 f4 brcc .+14 ; 0xefa 00000eec <__divmodsi4_neg2>: eec: 50 95 com r21 eee: 40 95 com r20 ef0: 30 95 com r19 ef2: 21 95 neg r18 ef4: 3f 4f sbci r19, 0xFF ; 255 ef6: 4f 4f sbci r20, 0xFF ; 255 ef8: 5f 4f sbci r21, 0xFF ; 255 00000efa <__divmodsi4_exit>: efa: 08 95 ret 00000efc <__divmodsi4_neg1>: efc: f6 f7 brtc .-4 ; 0xefa efe: 90 95 com r25 f00: 80 95 com r24 f02: 70 95 com r23 f04: 61 95 neg r22 f06: 7f 4f sbci r23, 0xFF ; 255 f08: 8f 4f sbci r24, 0xFF ; 255 f0a: 9f 4f sbci r25, 0xFF ; 255 f0c: 08 95 ret 00000f0e <__udivmodsi4>: f0e: a1 e2 ldi r26, 0x21 ; 33 f10: 1a 2e mov r1, r26 f12: aa 1b sub r26, r26 f14: bb 1b sub r27, r27 f16: fd 01 movw r30, r26 f18: 0d c0 rjmp .+26 ; 0xf34 00000f1a <__udivmodsi4_loop>: f1a: aa 1f adc r26, r26 f1c: bb 1f adc r27, r27 f1e: ee 1f adc r30, r30 f20: ff 1f adc r31, r31 f22: a2 17 cp r26, r18 f24: b3 07 cpc r27, r19 f26: e4 07 cpc r30, r20 f28: f5 07 cpc r31, r21 f2a: 20 f0 brcs .+8 ; 0xf34 f2c: a2 1b sub r26, r18 f2e: b3 0b sbc r27, r19 f30: e4 0b sbc r30, r20 f32: f5 0b sbc r31, r21 00000f34 <__udivmodsi4_ep>: f34: 66 1f adc r22, r22 f36: 77 1f adc r23, r23 f38: 88 1f adc r24, r24 f3a: 99 1f adc r25, r25 f3c: 1a 94 dec r1 f3e: 69 f7 brne .-38 ; 0xf1a f40: 60 95 com r22 f42: 70 95 com r23 f44: 80 95 com r24 f46: 90 95 com r25 f48: 9b 01 movw r18, r22 f4a: ac 01 movw r20, r24 f4c: bd 01 movw r22, r26 f4e: cf 01 movw r24, r30 f50: 08 95 ret 00000f52 : f52: 85 fd sbrc r24, 5 f54: 15 c0 rjmp .+42 ; 0xf80 00000f56 : f56: 80 62 ori r24, 0x20 ; 32 00000f58 : f58: 99 23 and r25, r25 f5a: 91 f4 brne .+36 ; 0xf80 f5c: 81 36 cpi r24, 0x61 ; 97 f5e: 84 f0 brlt .+32 ; 0xf80 f60: 8b 37 cpi r24, 0x7B ; 123 f62: 74 f4 brge .+28 ; 0xf80 f64: 08 95 ret 00000f66 : f66: 99 23 and r25, r25 f68: 59 f4 brne .+22 ; 0xf80 f6a: 80 33 cpi r24, 0x30 ; 48 f6c: 4c f0 brlt .+18 ; 0xf80 f6e: 8a 33 cpi r24, 0x3A ; 58 f70: 3c f4 brge .+14 ; 0xf80 f72: 08 95 ret 00000f74 : f74: 8f 93 push r24 f76: ef df rcall .-34 ; 0xf56 f78: 8f 91 pop r24 f7a: 09 f0 breq .+2 ; 0xf7e f7c: 80 62 ori r24, 0x20 ; 32 00000f7e <_tolower00>: f7e: 08 95 ret 00000f80 <__ctype_isfalse>: f80: 99 27 eor r25, r25 f82: 88 27 eor r24, r24 00000f84 <__ctype_istrue>: f84: 08 95 ret